2.4.6. Voltage selection links

Tile header HDRY and HDRX have an option for some of the interface signals to operate at a different signal level than the 3.3V default. The VDDIO_Y and VDDIO_X supplies are normally sourced from a Logic Tile or Core Tile attached to the IM-LT3. VDDIO_X and VDDIO_Y are connected to 3.3V by MOSFET transistors if no tile is present.VDDIO_X and VDDIO_Y can be manually connected to 3.3V by fitting resistor links on the PCB, but normally it is supplied only by the tile above See Voltage on header pins for details.

Resistor links R115 and R117 select between 3.3V and VDDIO_X for the SSRAM IO signal level and R117 and R118 select the SSRAM supply voltage. These resistors are fitted at manufacture to match the SSRAM present on the board.

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