3.3.1. PLD configuration

The IM-LT3 PLD is preloaded with a nonvolatile image.

In addition to control the loading of the FPGA image, the PLD also provides the nRTCKEN signal to the motherboard and the signals to control the isolation switches. The values for these signals are loaded serially from the FPGA after it has been configured. If you are not using the example FPGA design, you must include a design to perform the serial transfer at startup.

Note

The PLD can be programmed to directly control the bus break switches. The switches, however, are normally controlled by the FPGA sending serial configuration data to the PLD (see Isolation of HDRZ signals).

Caution

Loading an incorrect image into the PLD might render the board unusable. If the image in the PLD has been accidently erased, reload the image into the PLD by inserting the CONFIG link on the Interface Module and using the Progcards utility.

Table 3.2 lists the configuration signals that are received by the PLD at power on.

Table 3.2. Power-on configuration signals by clock cycle

ClockPLD data inputDescription
0 to nLOWLOW transmitted until FPGA ready to send data
n+1nRTCKENBypass control for JTAG return clock
n+2ZCTL[3]ZCTL data is clocked into the PLD and the state of the MANID links is clocked out of the PLD.
n+3ZCTL[2]
n+4ZCTL[1]
n+5ZCTL[0]
n+6HIGHIndicates end of transmitted data
-LOWLOW transmitted until system is reset.
Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DUI 0216B
Non-Confidential