| Copyright © 2005, 2006 ARM Limited. All rights reserved. | ARM DUI 0216B |
| Non-Confidential | |
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| Home > Hardware Description > Clock architecture > Clock routing to and from the IM-LT3 |
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The IM-LT3 clock signals are listed in Table 3.4. (For a description of JTAG clocks, see JTAG support.
Table 3.4. IM-LT3 clocks
| Signal | Source | Description |
|---|---|---|
| CLK_GLOBAL | Tile header HDRZ | A clock line common to the IM-LT3 and any tiles stacked on it. The FPGAs on all boards receive the clock as CKL_GLOBAL_IN. The FPGA on each Logic Tile outputs a CLK_GLOBAL_OUT signal to a tristate buffer. The signal CLK_GLOBAL_nEN enables the buffer and the local signal CLK_GLOBAL_OUT becomes the global clock for the system. NoteThe buffers are placed close to the HDRZ connectors, but there will be some skew between tiles. To use in-phase clock signals, use the CLK_POS_UP_OUT and CLK_NEG_UP_OUT clocks and the DLLs in the FPGAs to resynchronize the clock signals between tiles. |
| CLK_NEG_UP_OUT, CLK_POS_UP_OUT | IM-LT3 FPGA | Clock signal from FPGA to the tile stacked on top of the IM-LT3. These clocks can be configured as two independent clocks or one differential clock. These signals are typically outputs from the IM-LT3, but they can be configured as inputs and be driven by an attached Logic Tile. |
| SYSCLK0 | IM-LT3 FPGA or Integrator baseboard | This clock signal from the Integrator baseboard connects to the FPGA on the IM-LT3, but is not connected to any tiles in the stack. If the IM-LT3 is used with a Core Module but without a baseboard, this clock can be configured as an output from the FPGA to the Core Module. |
| SYSCLK[3:1] | IM-LT3 FPGA, tile header HDRZ, or Integrator baseboard | These clock signals are connected to the FPGA, the Integrator/CP motherboard, and the header connectors. SYSCLK[2:1] pass up to the first tile in the stack and SYSCLK[3] passes to the second tile in the stack. The IM-LT3 FPGA can accept or generate these clocks. These clocks are sometimes named HCLK[3:0] on Integrator Core Modules and baseboards. |
| R_CLK[2:0] | ICS307s | Locally generated programmable frequency clocks for the FPGA. |
| R_REF24MHZ | Crystal oscillator in ICS307 | Buffered versions of this reference signal are available as PLD_REF24MHZ and REF24MHZ. The 24MHz oscillator is the reference for all ICS307 devices. |
| DIMM_HCLK[4:1] | FPGA | These are the FPGA clocks to the SDRAM memory module. |
| RAM_SCLK | FPGA | This is the FPGA clock to the SSRAM memory. |
| LOOP[2:1] | FPGA | These clock loops enable FPGA to FPGA delay matching. See the Versatile/LT-XC2V4000+ User Guide for more information on clock matching. |
| XU[32] | FPGA or Core Tile | This clock might be used as the X_HCLK_DN output from the clock logic on the Core Tile. |
| XU[33] | FPGA or Core Tile | This clock might be used as the X_REFCLK_UP input to the clock logic on the Core Tile. |
| XU[34] | FPGA or Core Tile | This clock might be used as the X_HCLKIN_UP input to the clock logic on the Core Tile. |
| CLK_IN_PLUS[2:1], CLK_NEG_DN_IN, CLK_POS_DN_IN, and CLK_DN_THRU | Logic Tile | These Logic Tile clocks are not connected on the IM-LT3. |
| Copyright © 2005, 2006 ARM Limited. All rights reserved. | ARM DUI 0216B |
| Non-Confidential | |
| PDF version | |
| Home > Hardware Description > Clock architecture > Clock routing to and from the IM-LT3 |