4.2.1. Synthesis

The synthesis stage of the tool flow takes the HDL files (either VHDL, Verilog, or a combination) and compiles them into a netlist targeted at a particular technology. In the case of Xilinx Virtex, there are several synthesis tools available for both Windows and UNIX platforms, that provide support for a variety of programmable logic vendors.

Synthesis information is supplied either through a GUI front end, or in the form of a command-line script. The information typically includes:

Refer to the documentation for your particular software tool for further information.

A common netlist file format produced by synthesis is Electronic Data Interchange Format (EDIF) (for example, filename.edf). This file is used by the next stage of the tool flow, place and route.

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