4.2.2. Place and route

Place and route for the IM-LT3 FPGA is performed using Xilinx-specific software. This produces a .bit file that is used to program the FPGA. The .edf file is aimed at a particular device, taking into account the device size, package type, and speed grade.


Always specify CCLK as the start up clock for your design. The progcards utility automatically sets the startup clock to the JTAG clock option when you program the FPGA directly. Selecting CCLK ensures that the process always works for download into the FPGA or into flash.

Signal names from the top-level HDL are mapped onto actual device pins by a user constraints file .ucf. You can also specify the timing requirements within this file.


The pinout.ucf file for the complete FPGA pin allocation is supplied on the CD. This is intended as a starting point for any design, and must be edited before use in the place and route process.

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