Integrator ™/IM-LT3 UserGuideInterface Module
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Integrator ™/IM-LT3 UserGuide

Interface Module

Copyright © 2005, 2006 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this document
Intended audience
Organization
Typographical conventions
Further reading
Feedback
Feedback on this document
Feedback on the IM-LT3 InterfaceModule
1. Introduction
1.1. About the IM-LT3
1.2. IM-LT3 architecture
1.2.1. FPGA
1.2.2. Memory
1.2.3. Clocks
1.2.4. Expansion headers
1.2.5. Test and debug interfaces
1.2.6. Power supplies
1.3. Typical configurations
1.4. Precautions
1.4.1. Ensuring safety
1.4.2. Preventing damage
2. Getting Started
2.1. Using the IM-LT3 without a baseboard
2.1.1. Fitting a Core Module to the IM-LT3
2.1.2. SDRAM
2.1.3. Fitting a Core Tile to the IM-LT3
2.1.4. Fitting Logic Tiles to the IM-LT3
2.1.5. Fitting IT1 Interface Tiles to the IM-LT3
2.1.6. Supplying power to the IM-LT3
2.2. Using the IM-LT3 with an Integrator/CP
2.3. Connecting Multi-ICE,RealView ICE or Trace
2.3.1. Connecting Trace
2.4. Switches, links, and indicators
2.4.1. Image selector switches
2.4.2. User switches
2.4.3. CONFIG link
2.4.4. User LEDs
2.4.5. Status indicators
2.4.6. Voltage selection links
3. Hardware Description
3.1. Differences between IM-LT3 andIM-LT1
3.2. FPGA
3.3. PLD circuitry
3.3.1. PLD configuration
3.4. Reset control
3.5. Header connectors
3.5.1. Voltage on header pins
3.5.2. Isolation of HDRZ signals
3.6. Clock architecture
3.6.1. Clock routing to and from the IM-LT3
3.6.2. ICS307 clock generators
3.7. Memory interfaces
3.7.1. SDRAM interface
3.7.2. ZBT SSRAM interface
3.8. JTAG support
3.8.1. JTAG connection
3.8.2. JTAG connection modes
3.8.3. JTAG signals
3.8.4. JTAG scan paths
3.8.5. Integrated logic analyzer
3.9. Switches and LEDs
3.10. Test points
3.10.1. Debug connectors
4. Configuring the FPGA and PLD
4.1. FPGA configuration system architecture
4.2. FPGA tool flow
4.2.1. Synthesis
4.2.2. Place and route
4.3. Configuring the FPGA from flash
4.4. Loading new FPGA configurations
4.4.1. Reconfiguring the FPGA directly
4.4.2. Downloading new the FPGA configurationsinto flash
4.5. Reprogramming the PLD
A. Signal Descriptions
A.1. HDRY tile connector
A.2. HDRX tile connector
A.3. HDRZ tile connector
A.4. HDRA Integrator connector
A.5. HDRB Integrator connector
A.5.1. HDRB signal descriptions
A.6. JTAG connector signals
A.7. Integrated logic analyzer connectorsignals
A.8. Mictor logic analyzer connectors
B. Specifications
B.1. Electrical specification
B.1.1. Bus interface characteristics
B.1.2. Current requirements
B.2. Mechanical details
C. Using a Core Tile and an IM-LT3 as a Core Module
C.1. About the system architecture
C.1.1. Integrator/CP system buses
C.1.2. Configuring little or big-endian operation
C.2. Module ID selection and interruptrouting
C.3. Top level memory map
C.3.1. Physical location of memory chips
C.3.2. Configurable area of memory map
C.3.3. Baseboard flash memory
C.3.4. Memory timing
C.4. Programmable logic
C.4.1. Baseboard system support PLD
C.4.2. System controller FPGA
C.4.3. HDL files
C.5. Register and memory overview
C.5.1. CM control registers for Integrator/CP
C.6. Peripherals and interfaces
C.6.1. Clock control
C.6.2. Counter/timers
C.6.3. Real-time clock
C.6.4. UARTs
C.6.5. Keyboard and mouseinterface
C.6.6. MMC interface
C.6.7. Audio interface
C.6.8. Touchscreen controller interface
C.6.9. Display interface
C.6.10. Ethernet interface
C.7. Reset controller
C.7.1. Reset control signals
C.7.2. Software resets
C.8. Interrupt control
C.8.1. Interrupt controllers
C.8.2. Interrupt routing
C.8.3. CP image interruptcontrol registers
C.8.4. Handling interrupts

List of Figures

1.1. Integrator/IM-LT3 Interface Modulelayout
1.2. ARM Integrator IM-LT3 block diagram
1.3. Integrator/CP system
2.1. IM-LT3 and Core Module
2.2. IM-LT3 and Core TIle
2.3. IM-LT3 and Logic Tile
2.4. IM-LT3, Core Tile, Logic Tileand Interface TIle
2.5. Power connector on IM-LT3
2.6. Integrator/CP with IM-LT3 and Core Tile
2.7. CP with Core Module, IM-LT3, and Logic Tile
2.8. Multi-ICE connection to the InterfaceModule
2.9. Trace connection
2.10. Links, switches, and indicators
3.1. IM-LT3 block diagram
3.2. PLD logic and FPGA configuration
3.3. Reset control
3.4. Reset sequence timing
3.5. Voltages present on tile connectorblades
3.6. Isolation switches
3.7. Clock signal routing (Core Module)
3.8. Clock signal routing (Core Tile)
3.9. Programmable clock generators
3.10. VCO configuration data
3.11. SDRAM clock and control signals
3.12. SSRAM clock and control signals
3.13. JTAG connector, CFGEN link, and LED
3.14. JTAG connector pinout
3.15. JTAG data path block diagram (CoreModule)
3.16. JTAG data path block diagram (CoreTile)
3.17. Simplified view of data path in debugmode (Core Module)
3.18. Simplified view of data path in debugmode (Core Tile)
3.19. JTAG clock path (Core Module)
3.20. JTAG clock path (Core Tile)
3.21. TMS path (Core Module)
3.22. TMS path (Core Tile)
3.23. Switch and LED block diagram
3.24. Switch and LED location
3.25. Test points
3.26. Trace and Logic analyzer connectionblock diagram
4.1. Basic tool flow
A.1. 180-pin Samtec connector
A.2. 300-pin Samtec connector
A.3. HDRA socket pin numbering
A.4. HDRB socket pin numbering (X-rayview)
A.5. Multi-ICE JTAG connector
A.6. Embedded logic analyzer connectorJ33
A.7. Mictor connector pinout
B.1. Board dimensions (top view)
B.2. Board dimensions (bottom view)
C.1. Integrator/CP system architecture
C.2. Bus routing between CP baseboard,Core Tile, and IM-LT3
C.3. APB peripherals
C.4. Top-level memory map
C.5. Physical location of memory
C.6. Baseboard PLD
C.7. System controllerFPGA block diagram
C.8. CM_CTRL
C.9. IM-LT3 reset controller
C.10. Interrupt architecture (CP image)
C.11. Interrupt signal routing with CoreModule
C.12. Interrupt signal routing for tiles

List of Tables

1.1. Typical configurations
2.1. LED functional summary
3.1. Differences between IM-LT1 and IM-LT3
3.2. Power-on configuration signals by clock cycle
3.3. Reset signal descriptions
3.4. IM-LT3 clocks
3.5. Output Divider code
3.6. JTAG signal description
3.7. Test point functions
4.1. Image selection
A.1. HDRY signals
A.2. HDRX signals
A.3. HDRZ signals
A.4. Bus bit assignment
A.5. HDRB signal description (AHB)
A.6. Trace/Debug connector (J11)
A.7. Debug connector (J4)
B.1. IM-LT3 electrical characteristics
B.2. Current requirements
C.1. Example of 32KB TCM
C.2. Example of TCM disabled or no TCM
C.3. Wait states for memory access
C.4. IM-LT3 FPGA image functional FPGA block HDL file descriptions
C.5. System control register map
C.6. Core Module status, control, and interrupt registers
C.7. CM_CTRL register
C.8. Reset signal descriptions
C.9. Primary interrupt register addresses
C.10. Primary interrupt register bit assignments
C.11. IRQ and FIQ register bit assignment
C.12. Secondary interrupt register addresses
C.13. IRQ register bit assignment

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt frompart 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The IM-LT3 Interface Module generates, uses, and can radiateradio frequency energy and may cause harmful interference to radiocommunications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment causesharmful interference to radio or television reception, which canbe determined by turning the equipment off or on, you are encouragedto try to correct the interference by one or more of the followingmeasures:

  • ensureattached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment andthe receiver

  • connect the equipment into an outlet on a circuitdifferent from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technicianfor help

Note

It is recommended that wherever possible shielded interfacecables be used.

Revision History
Revision A 21January 2005 New document
Revision B 20July 2006 New document
Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DUI 0216B
Non-Confidential
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