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The PB926EJ-S status and system control registers enable
the processor to determine its environment and to control some on-board
operations. The registers, listed in Table 4.4, are located from 0x10000000.
See also the ARM PrimeCell System Controller (SP810) Technical Reference Manual for details of control registers in the SP810 System Controller that is in the ARM926EJ-S PXP Development Chip. See also Reset controller for a description of the reset logic.
All registers are 32 bits wide and do not support byte writes. Write operations must be word-wide. Bits marked as reserved in the following sections must be preserved using read-modify-write operations.
In Table 4.4, the entry for Reset Level indicates the highest reset level that modifies its contents:
This a programmable reset level that is triggered by a software reset, nSRST, P_nRST, or nPBRESET. See Reset controller for a description of programmable reset levels and the reset signals.
Pressing the SDC RECONFIG button drives the nPBSDCRECONFIG signal active and initiates reconfiguration. The registers are loaded from a writable configuration register. For example, configuration loads the OSC0 clock values from SYS_OSCRESET0. This allows the clock to be changed for testing new divider values. A hard reset of level 0 resets both the OSC0 and SYS_OSCRESET0 registers to the hard-wired default values.
Pressing the FPGA CONFIG initiates reconfiguration of the FPGA.
The system power on reset (nSYSPOR) is a level 0 reset and initializes all registers to their default value.
Table 4.4. Register map for system control registers
| Name | Address | Access[a] | Reset level | Description |
|---|---|---|---|---|
| SYS_ID | 0x10000000 | Read only | - | System Identity. See ID Register, SYS_ID. |
| SYS_SW | 0x10000004 | Read only | - | Bits [7:0] map to S6 (user switches) |
| SYS_LED | 0x10000008 | Read/Write | 6 | Bits [7:0] map to user LEDs (located next to S6) |
| SYS_OSC0 | 0x1000000C | Read/Write Lockable | 2 | Settings for the ICS307 programmable oscillator chip OSC0. This oscillator provides the PLLCLKEXT and XTALCLKEXT signal sources. See Oscillator registers, SYS_OSCx and ARM926EJ-S PXP Development Chip clocks. |
| SYS_OSC1 | 0x10000010 | Read/Write Lockable | 2 | Settings for the ICS307 programmable oscillator chip OSC1. This oscillator provides the HCLKM1 signal source. |
| SYS_OSC2 | 0x10000014 | Read/Write Lockable | 2 | Settings for the ICS307 programmable oscillator chip OSC2. This oscillator provides the HCLKM2 signal source. |
| SYS_OSC3 | 0x10000018 | Read/Write Lockable | 2 | Settings for the ICS307 programmable oscillator chip OSC3. This oscillator provides the HCLKS signal source. |
| SYS_OSC4 | 0x1000001C | Read/Write Lockable | 2 | Settings for the ICS307 programmable oscillator chip OSC4. This oscillator provides the CLCDCLKEXT signal source. |
| SYS_LOCK | 0x10000020 | Read/Write | 6 | Write 0xA05F to unlock.
See Lock Register, SYS_LOCK. |
| SYS_100HZ | 0x10000024 | Read only | 0 | 100Hz counter. |
| SYS_CFGDATA1 | 0x10000028 | Read/Write Lockable | 0 | Configuration data to be applied to HDATAM1 pins at power on or when the SDC CONFIG pushbutton is pressed. |
| SYS_CFGDATA2 | 0x1000002C | Read/Write Lockable | 0 | Configuration data to be applied to HDATAM2 pins at power on or when the SDC CONFIG pushbutton is pressed. |
| SYS_FLAGS | 0x10000030 | Read only | 6 | General-purpose flags (reset by any reset). See Flag registers, SYS_FLAGx and SYS_NVFLAGx. |
| SYS_FLAGSSET | 0x10000030 | Write | 6 | Set bits in general-purpose flags. |
| SYS_FLAGSCLR | 0x10000034 | Write | 6 | Clear bits in general-purpose flags. |
| SYS_NVFLAGS | 0x10000038 | Read only | 0 | General-purpose nonvolatile flags (reset only on power up). |
| SYS_NVFLAGSSET | 0x10000038 | Write | 0 | Set bits in general-purpose nonvolatile flags. |
| SYS_NVFLAGSCLR | 0x1000003C | Write | 0 | Clear bits in general-purpose nonvolatile flags. |
| SYS_RESETCTL | 0x10000040 | Read/Write Lockable | 0 | The reset control register sets reset depth and programmable soft reset. |
| SYS_PCICTL | 0x10000044 | Read only | - | Read returns a HIGH in bit [0] if a PCI board is present in the expansion backplane. |
| SYS_MCI | 0x10000048 | Read only | - | Contains the “card present” and “write enabled” status for the MMCI0 and MMCI1 cards |
| SYS_FLASH | 0x1000004C | Read/Write | 6 | Controls write protection of flash devices. |
| SYS_CLCD | 0x10000050 | Read/Write | 6 | Controls LCD power and multiplexing. |
| SYS_CLCDSER | 0x10000054 | Read/Write | 6 | Control interface to activate the 2.2 inch display on the LCD adaptor. |
| SYS_BOOTCS | 0x10000058 | Read only | - | Contains the settings of the boot switch S1. |
| SYS_24MHz | 0x1000005C | Read only | 6 | 32-bit counter clocked at 24MHz. |
| SYS_MISC | 0x10000060 | Read only | 6 | See Miscellaneous System Control Register, SYS_MISC for details. |
| SYS_DMAPSR0 | 0x10000064 | Read/Write | 6 | Selection control for remapping DMA from external peripherals to DMA channel 0. |
| SYS_DMAPSR1 | 0x10000068 | Read/Write | 6 | Selection control for remapping DMA from external peripherals to DMA channel 1. |
| SYS_DMAPSR2 | 0x1000006C | Read/Write | 6 | Selection control for remapping DMA from external peripherals to DMA channel 1. |
| SYS_OSCRESET0 | 0x1000008C | Read/Write Lockable | 0 | Value to load into the SYS_OSC0 register if the DEV CHIP RECONFIGURE pushbutton is pressed (APPLYCFGWORD active). At power-on reset, the SYS_OSCRESET0 is loaded with the same default value as used for SYS_OSC0. |
| SYS_OSCRESET1 | 0x10000090 | Read/Write Lockable | 0 | Value to load into the SYS_OSC1 register if the DEV CHIP RECONFIGURE pushbutton is pressed (APPLYCFGWORD active). At power-on reset, the SYS_OSCRESET1 is loaded with the same default value as used for SYS_OSC1. |
| SYS_OSCRESET2 | 0x10000094 | Read/Write Lockable | 0 | Value to load into the SYS_OSC2 register if the DEV CHIP RECONFIGURE pushbutton is pressed (APPLYCFGWORD active). At power-on reset, the SYS_OSCRESET2 is loaded with the same default value as used for SYS_OSC2. |
| SYS_OSCRESET3 | 0x10000098 | Read/Write Lockable | 0 | Value to load into the SYS_OSC3 register if the DEV CHIP RECONFIGURE pushbutton is pressed (APPLYCFGWORD active). At power-on reset, the SYS_OSCRESET3 is loaded with the same default value as used for SYS_OSC3. |
| SYS_OSCRESET4 | 0x1000009C | Read/Write Lockable | 0 | Value to load into the SYS_OSC4 register if the DEV CHIP RECONFIGURE pushbutton is pressed (APPLYCFGWORD active). At power-on reset, the SYS_OSCRESET4 is loaded with the same default value as used for SYS_OSC4. |
| SYS_TEST_OSC0 | 0x100000C0 | Read only | 6 | 32-bit counter clocked from ISC307 clock 0. |
| SYS_TEST_OSC1 | 0x100000C4 | Read only | 6 | 32-bit counter clocked from ISC307 clock 1. |
| SYS_TEST_OSC2 | 0x100000C8 | Read only | 6 | 32-bit counter clocked from ISC307 clock 2. |
| SYS_TEST_OSC3 | 0x100000CC | Read only | 6 | 32-bit counter clocked from ISC307 clock 3. |
| SYS_TEST_OSC4 | 0x100000D0 | Read only | 6 | 32-bit counter clocked from ISC307 clock 4. |
[a] If Access is lockable, the register can only be written if SYS_LOCK is unlocked (see Lock Register, SYS_LOCK). | ||||
| Copyright © 2003-2010 ARM Limited. All rights reserved. | ARM DUI 0224I |
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| Home > Programmer’s Reference > Status and system control registers |