4.11.1. Primary interrupt controller

The primary interrupt control registers are listed in Table 4.39. For more detail on the primary interrupt controller, see the ARMPL190 VIC Technical Reference Manual.

Table 4.39. Primary interrupt controller registers

Address

Name

Access

Description

0x10140000

PICIRQStatus

Read

IRQ status register

0x10140004

PICFIQStatus

Read

FIQ status register

0x10140008

PICRawIntr

Read

Raw interrupt status register

0x1014000C

PICIntSelect

Read/write

Interrupt select register

0x10140010

PICIntEnable

Read/write

Interrupt enable register

0x10140014

PICIntEnClear

Write

Interrupt enable clear register

0x10140018

PICSoftInt

Read/write

Software interrupt register

0x1014001C

PICSoftIntClear

Write

Software interrupt clear register

0x10140020

PICProtection

Read/write

Protection enable register

0x10140030

PICVectAddr

Read/write

Vector address register

0x10140034

PICDefVectAddr

Read/write

Default vector address register

0x10140100-

0x1014013C

PICVectAddr0- PICVectAddr15

Read/write

Vector address 0 register to Vector address 15 register

0x10140200-

0x1014023C

PICVectCntl0- PICVectCntl15

Read/write

Vector control 0 register to Vector control 15 register

0x10140300- 0x10140310

PICITCR, PICITIP1, PICITIP2, PICITOP1, PICITOP2,

Read/write

Test control registers

0x10140FE0- 0x10140FEC

PICPeriphID0- PICPeriphID3

Read

Peripheral identification registers

0x10140FF0- 0x10140FFC

PICPCellID0- PICPCellID3

Read

PrimeCell identification registers


The bit assignments for the primary interrupt controller are shown in Figure 4.22 and Table 4.40. Each bit corresponds to an interrupt source. Use the bit to enable or disable the interrupt or to check the interrupt status.

Figure 4.22. Primary interrupt registers


Table 4.40. Interrupt signals to primary interrupt controller

BitInterrupt source[a]Description
[31]VICINTSOURCE31External interrupt from secondary controller
[30]VICINTSOURCE30External interrupt signal from RealView Logic Tile or PCI3 interrupt signal
[29]VICINTSOURCE29External interrupt signal from RealView Logic Tile or PCI2 interrupt signal
[28]VICINTSOURCE28External interrupt signal from RealView Logic Tile or PCI1 interrupt signal
[27]VICINTSOURCE27External interrupt signal from RealView Logic Tile or PCI0 interrupt signal
[26]VICINTSOURCE26External interrupt signal from RealView Logic Tile or USB interrupt signal
[25]VICINTSOURCE25External interrupt signal from RealView Logic Tile or ETHERNET interrupt signal
[24]VICINTSOURCE24External interrupt signal from RealView Logic Tile or AACI interrupt signal
[23]VICINTSOURCE23External interrupt signal from RealView Logic Tile or MCI1A interrupt signal
[22]VICINTSOURCE22External interrupt signal from RealView Logic Tile or MCI0A interrupt signal
[21]VICINTSOURCE21External interrupt signal from RealView Logic Tile or DiskOnChip interrupt signal
[20]GNDReserved
[19]MBXGraphics processor on development chip
[18]PWRFAILPower failure from FPGA
[17]DMADMA controller in development chip
[16]CLCDCLCD controller in development chip
[15]SCI0Smart Card interface in development chip
[14]UART2UART2 on development chip
[13]UART1UART1 on development chip
[12]UART0UART0 on development chip
[11]SSPSynchronous serial port in development chip
[10]RTCReal time clock in development chip
[9]GPIO3GPIO controller in development chip
[8]GPIO2GPIO controller in development chip
[7]GPIO1GPIO controller in development chip
[6]GPIO0GPIO controller in development chip
[5]Timer 2 or 3Timers on development chip
[4]Timer 0 or 1Timers on development chip
[3]Comms TX

Debug communications transmit interrupt.

This interrupt indicates that the communications channel is available for the processor to pass messages to the debugger.

[2]Comms RX

Debug communications receive interrupt.

This interrupt indicates to the processor that messages are available for the processor to read.

[1]Software interrupt

Software interrupt. Enabling and disabling the software interrupt is done with the Enable Set and Enable Clear Registers. Triggering the interrupt however, is done from the Soft Interrupt Set register.

[0]WatchdogWatchdog timer

[a] The VICINTSOURCEx signals are external to the ARM926EJ-S PXP Development Chip.


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