RealView Platform Baseboard for ARM926EJ-S User GuideHBI-0117
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RealView Platform Baseboard for ARM926EJ-S™ User Guide

HBI-0117

Copyright © 2003-2010 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the PB926EJ-S
1.2. PB926EJ-S architecture
1.2.1. System architecture
1.2.2. ARM926EJ-S PXP Development Chip
1.2.3. PB926EJ-S FPGA
1.2.4. Displays
1.2.5. RealView Logic Tile expansion
1.2.6. Memory
1.2.7. Clock generators
1.2.8. Debug and test interfaces
1.3. Precautions
1.3.1. Ensuring safety
1.3.2. Preventing damage
2. Getting Started
2.1. Setting up the RealView Platform
2.2. Setting the configuration switches
2.2.1. Boot memory configuration
2.2.2. LED indicators
2.2.3. Boot Monitor configuration
2.3. Connecting JTAG debugging equipment
2.4. Connecting the Trace Port Analyzer
2.4.1. About using trace
2.5. Supplying power
2.6. Using the PB926EJ-S Boot Monitor and platform library
2.6.1. Running the Boot Monitor
2.6.2. Rebuilding the Boot Monitor
2.6.3. Loading Boot Monitor into NOR flash
2.6.4. Redirecting character output to hardware devices
2.6.5. Rebuilding the platform library
2.6.6. Building an application with the platform library
2.6.7. Loading and running an application from NOR flash
2.6.8. Using a boot script to run an image automatically
3. Hardware Description
3.1. ARM926EJ-S PXP Development Chip
3.1.1. ARM926EJ-S PXP Development Chip overview
3.1.2. Configuration control
3.1.3. AHB bridges and the bus matrix
3.1.4. Memory interface
3.1.5. AHB monitor
3.2. FPGA
3.2.1. FPGA configuration
3.3. Reset controller
3.3.1. Reset and reconfiguration logic
3.3.2. Reset level
3.3.3. Memory aliasing at reset
3.3.4. Reset signals
3.3.5. Reset timing
3.4. Power supply control
3.5. Clock architecture
3.5.1. ARM926EJ-S PXP Development Chip clocks
3.5.2. RealView Logic Tile clocks
3.5.3. Peripheral clocks
3.5.4. Clock multiplexor logic
3.6. Advanced Audio Codec Interface, AACI
3.7. Character LCD controller
3.8. CLCDC interface
3.9. DMA
3.10. Ethernet interface
3.10.1. About the SMSC LAN91C111
3.11. GPIO interface
3.12. Interrupts
3.13. Keyboard/Mouse Interface, KMI
3.14. Memory Card Interface, MCI
3.14.1. MMC or SD operation
3.14.2. Card insertion and removal
3.14.3. Card interface description
3.15. PCI interface
3.16. Serial bus interface
3.17. Smart Card interface, SCI
3.18. Synchronous Serial Port, SSP
3.19. User switches and LEDs
3.20. UART interface
3.21. USB interface
3.22. Test, configuration, and debug interfaces
3.22.1. JTAG and USB debug port support
3.22.2. ChipScope integrated logic analyzer
3.22.3. Embedded trace support
4. Programmer’s Reference
4.1. Memory map
4.2. Configuration and initialization
4.2.1. Remapping of boot memory
4.2.2. Memory characteristics
4.3. Status and system control registers
4.3.1. ID Register, SYS_ID
4.3.2. Switch Register, SYS_SW
4.3.3. LED Register, SYS_LED
4.3.4. Oscillator registers, SYS_OSCx
4.3.5. Lock Register, SYS_LOCK
4.3.6. 100Hz Counter, SYS_100HZ
4.3.7. Configuration registers SYS_CFGDATAx
4.3.8. Flag registers, SYS_FLAGx and SYS_NVFLAGx
4.3.9. Reset Control Register, SYS_RESETCTL
4.3.10. PCI Control Register, SYS_PCICTL
4.3.11. MCI Register, SYS_MCI
4.3.12. Flash Control Register, SYS_FLASH
4.3.13. CLCD Control Register, SYS_CLCD
4.3.14. 2.2 inch LCD Control Register SYS_CLCDSER
4.3.15. Boot Select Register, SYS_BOOTCS
4.3.16. 24MHz Counter, SYS_24MHZ
4.3.17. Miscellaneous System Control Register, SYS_MISC
4.3.18. DMA peripheral map registers, SYS_DMAPSRx
4.3.19. Oscillator reset registers, SYS_OSCRESETx
4.3.20. Oscillator test registers, SYS_TEST_OSCx
4.4. AHB monitor
4.5. Advanced Audio CODEC Interface, AACI
4.5.1. PrimeCell Modifications
4.6. Character LCD display
4.7. Color LCD Controller, CLCDC
4.7.1. PrimeCell Modifications
4.7.2. Display resolutions and display memory organization
4.8. Direct Memory Access Controller and mapping registers
4.9. Ethernet
4.10. General Purpose Input/Output, GPIO
4.11. Interrupt controllers
4.11.1. Primary interrupt controller
4.11.2. Secondary interrupt controller
4.11.3. Handling interrupts
4.12. Keyboard and Mouse Interface, KMI
4.13. MBX
4.14. MOVE video coprocessor
4.15. MultiMedia Card Interfaces, MCIx
4.16. MultiPort Memory Controller, MPMC
4.16.1. Register values
4.17. PCI controller
4.17.1. Control registers
4.17.2. PCI configuration
4.18. Real Time Clock, RTC
4.19. Serial bus interface
4.20. Smart Card Interface, SCI
4.21. Synchronous Serial Port, SSP
4.22. Synchronous Static Memory Controller, SSMC
4.22.1. Register values
4.23. System Controller
4.24. Timers
4.25. UART
4.25.1. PrimeCell Modifications
4.26. USB interface
4.27. Vector Floating Point, VFP9
4.28. Watchdog
A. Signal Descriptions
A.1. Synchronous Serial Port interface
A.2. Smart Card interface
A.3. UART interface
A.4. USB interface
A.5. Audio CODEC interface
A.6. MMC and SD flash card interface
A.7. CLCD display interface
A.8. VGA display interface
A.9. GPIO interface
A.10. Keyboard and mouse interface
A.11. Ethernet interface
A.12. RealView Logic Tile header connectors
A.12.1. HDRX signals
A.12.2. HDRY signals
A.12.3. HDRZ
A.13. Test and debug connections
A.13.1. Overview of test points
A.13.2. JTAG
A.13.3. USB debug port
A.13.4. Trace connector pinout
A.13.5. Embedded logic analyzer
A.13.6. AHB monitor
A.13.7. FPGA debug connector pinout
B. Specifications
B.1. Electrical specification
B.1.1. Bus interface characteristics
B.1.2. Current requirements
B.2. Clock rate restrictions
B.2.1. AHB bus timing
B.2.2. Memory timing
B.2.3. Peripheral timing
B.3. Mechanical details
C. CLCD Display and Adaptor Board
C.1. About the CLCD display and adaptor board
C.2. Installing the CLCD display
C.2.1. Configuration
C.2.2. LCD power control
C.3. Touchscreen controller interface
C.3.1. Touchscreen interface architecture
C.3.2. Touchscreen controller programmer’s interface
C.4. Connectors
C.4.1. Interface connector
C.4.2. LCD prototyping connector
C.4.3. Touchscreen prototyping connector
C.4.4. Inverter prototyping connector
C.4.5. A/D and keypad connector
C.5. Mechanical layout
D. PCI Backplane and Enclosure
D.1. Connecting the PB926EJ-S to the PCI enclosure
D.1.1. Setting the backplane configuration switches
D.1.2. Connecting two PB926EJ-S boards
D.2. Backplane hardware
D.2.1. JTAG signals
D.3. Connectors
D.3.1. Power connector
D.3.2. Logic analyzer connector
D.3.3. JTAG connector
E. Memory Expansion Boards
E.1. About memory expansion
E.1.1. Operation without expansion memory
E.1.2. Memory board configuration
E.2. Fitting a memory board
E.3. EEPROM contents
E.4. Connector pinout
E.4.1. Expansion connector
E.5. Mechanical layout
F. RealView Logic Tile
F.1. About the RealView Logic Tile
F.2. Fitting a RealView Logic Tile
F.3. Header connectors
F.3.1. JTAG
F.3.2. Variable I/O levels
F.3.3. RealView Logic Tile I/O
F.3.4. RealView Logic Tile clocks
F.3.5. AHB buses used by the FPGA and RealView Logic Tiles
F.3.6. Reset
G. Configuring the USB Debug Connection
G.1. Installing the RealView ICE Micro Edition driver
G.1.1. Installing the RealView Developer Suite
G.1.2. Installing the RealView ICE Micro Edition driver on Windows 98SE
G.1.3. Installing the RealView ICE Micro Edition driver on Windows 2000
G.1.4. Installing the RealView ICE Micro Edition driver on Windows XP Professional
G.2. Changes to RealView Debugger
G.3. Using the USB debug port to connect RealView Debugger
G.3.1. Configuration
G.4. Using the Debug tab of the RealView Debugger Register pane
G.4.1. Global Properties
G.4.2. Device Properties
G.4.3. Semihosting Properties

List of Figures

1. Key to timing diagram conventions
1.1. PB926EJ-S layout
1.2. PB926EJ-S block diagram
2.1. Location of S1-1 and S6-1
2.2. JTAG connection
2.3. USB debug port connection
2.4. Example of MultiTrace and JTAG connection
2.5. Example of RealView ICE and RealView Trace
2.6. Power connectors
3.1. ARM926EJ-S PXP Development Chip block diagram
3.2. Configuration signals from SYS_CFGDATAx
3.3. Example of multiple masters
3.4. AHB map
3.5. Core APB and DMA APB map
3.6. Memory devices
3.7. AHB monitor connection
3.8. FPGA block diagram
3.9. FPGA configuration
3.10. FPGA reload sequence
3.11. PB926EJ-S reset logic
3.12. Reset signal sequence
3.13. Programmable reset level
3.14. Boot memory remap logic
3.15. Power-on reset and configuration timing
3.16. Standby switch and power-supply control
3.17. Clock architecture
3.18. ARM926EJ-S PXP Development Chip internal multiplexors
3.19. Default clock sources and frequencies
3.20. Clock sources for asynchronous AHB bridges
3.21. Serial data and SYS_OSCx register format
3.22. Example of selecting a tile clock for the AHB S bridge
3.23. Clock multiplexors
3.24. Audio interface
3.25. Character display
3.26. Display interface
3.27. DMA channels
3.28. Ethernet interface architecture
3.29. GPIO block diagram
3.30. External and internal interrupt sources
3.31. KMI block diagram
3.32. MMI interface
3.33. PCI bridge
3.34. Serial bus block diagram
3.35. SCI block diagram
3.36. SSP block diagram
3.37. Switch and LED interface
3.38. UARTs block diagram
3.39. UART0 interface
3.40. Simplified interface for UART[3:1]
3.41. OTG243 block diagram
3.42. Test and debug connectors, links, and LEDs
3.43. JTAG connector signals
3.44. JTAG signal routing
3.45. RealView Logic Tile JTAG circuitry
4.1. ARM Data bus memory map
4.2. Booting from NOR flash 1
4.3. Booting from static expansion memory
4.4. Booting from AHB expansion
4.5. ID Register, SYS_ID
4.6. SYS_SW
4.7. SYS_LED
4.8. Oscillator Register, SYS_OSCx
4.9. Lock Register, SYS_LOCK
4.10. SYS_CFGDATA1
4.11. SYS_CFGDATA2
4.12. SYS_RESETCTL
4.13. SYS_MCI
4.14. SYS_CLCD
4.15. SYS_CLCDSER
4.16. SYS_BOOTCS
4.17. SYS_MISC
4.18. DMA mapping register
4.19. Oscillator Register, SYS_OSCRESETx
4.20. AACI ID register
4.21. SYS_DMAP0-2 mapping register format
4.22. Primary interrupt registers
4.23. Secondary interrupt registers
4.24. AHB M2 to PCI mapping
4.25. PCI_IMAPx register
4.26. PCI_SELFID register
4.27. PCI_FLAGS register
4.28. PCI to AHB S mapping
4.29. PCI_SMAPx register
A.1. SSP expansion interface
A.2. Smartcard contacts assignment
A.3. J28 SCI expansion
A.4. Serial connector
A.5. USB interfaces
A.6. Audio connectors
A.7. MMC/SD card socket pin numbering
A.8. MMC card
A.9. CLCD Interface connector J18
A.10. VGA connector J19
A.11. GPIO connector
A.12. KMI connector
A.13. Ethernet connector J5
A.14. HDRX, HDRY, and HDRZ (upper) pin numbering
A.15. Test points and debug connectors
A.16. Multi-ICE JTAG connector J31
A.17. USB debug connector J30
A.18. Embedded logic analyzer connector J33
A.19. AMP Mictor connector
B.1. Baseboard mechanical details
C.1. CLCD adaptor board connectors (bottom view)
C.2. Small CLCD enclosure
C.3. Large CLCD enclosure
C.4. Displays mounted directly onto top of adaptor board.
C.5. CLCD adaptor board connection
C.6. CLCD buffer and power supply control links
C.7. Touchscreen and keypad interface
C.8. Touchscreen resistive elements
C.9. CLCD adaptor board mechanical layout
D.1. Installing the platform board into the PCI enclosure
D.2. Multiple boards on PCI bus
D.3. PCI backplane
D.4. JTAG signal flow on the PCI backplane
D.5. AMP Mictor connector J4
D.6. PCI expansion board JTAG connector J5
E.1. Dynamic memory board block diagram
E.2. Static memory board block diagram
E.3. Memory board installation locations
E.4. Chip select information block
E.5. Samtec connector
E.6. Dynamic memory board layout
E.7. Static memory board layout
F.1. Signals on the RealView Logic Tile expansion connectors
F.2. RealView Logic Tile fitted on PB926EJ-S
F.3. HDRX, HDRY, and HDRZ (upper) pin numbering
F.4. RealView Logic Tile tristate for I/O
F.5. Clock signals and the RealView Logic Tile
F.6. Bus signals for RealView Logic Tile and FPGA
G.1. Nodes added to Connection Control window
G.2. The Connection Control window
G.3. ARM926EJ-S PXP Development Chip detected
G.4. Error shown when unpowered devices are detected
G.5. Error shown when no devices are detected
G.6. Error shown when the USB debug port is not functioning
G.7. Connection Properties window
G.8. The Debug tab of the Register pane

List of Tables

2.1. Selecting the boot device
2.2. Default switch positions
2.3. LED Indicators
2.4. Boot Monitor commands
2.5. Boot Monitor Configure commands
2.6. Boot Monitor Debug commands
2.7. Boot Monitor NOR flash commands
3.1. Configuration switch S1
3.2. FPGA image selection
3.3. Reset sources and effects
3.4. Reset signal descriptions
3.5. ARM926EJ-S PXP Development Chip clocks
3.6. Asynchronous clock signals
3.7. HCLKM1 selection
3.8. HCLKM2 selection
3.9. HCLKS selection
3.10. GLOBALCLK selection
3.11. PB926EJ-S clocks and clock control signals
3.12. Audio system specification
3.13. AC’97 audio debug signals on J45
3.14. Display interface signals
3.15. DMA signals for external devices
3.16. Ethernet signals
3.17. MMC/SD interface signals
3.18. MMC signals
3.19. Serial bus addresses
3.20. Serial bus signals
3.21. Smart Card interface signals
3.22. SSP signal descriptions
3.23. Serial interface signal assignment
3.24. USB interface signal assignment
3.25. JTAG related signals
4.1. Memory map
4.2. Selecting the boot device
4.3. Memory chip selects and address range
4.4. Register map for system control registers
4.5. ID Register, SYS_ID bit assignment
4.6. Oscillator Register, SYS_OSCx bit assignment
4.7. Lock Register, SYS_LOCK bit assignment
4.8. Configuration register 1
4.9. Configuration register 2
4.10. Flag registers
4.11. Reset level control
4.12. MCI control
4.13. Flash control
4.14. SYS_CLCD register
4.15. SYS_CLCDSER register
4.16. BOOT configuration switches
4.17. SYS_MISC
4.18. DMA map registers
4.19. SYS_DMAPSRx, DMA mapping register format
4.20. Oscillator test registers
4.21. AHB monitor implementation
4.22. AACI implementation
4.23. Modified AACI PeriphID3 register
4.24. Character LCD display implementation
4.25. Character LCD control and data registers
4.26. Character LCD display commands
4.27. CLCDC implementation
4.28. PrimeCell CLCDC register differences
4.29. Values for different display resolutions
4.30. Assignment of display memory to R[7:0], G[7:0], and B[7:0]
4.31. PL110 hardware playback mode
4.32. DMAC implementation
4.33. DMA channels
4.34. DMA mapping register format
4.35. Ethernet implementation
4.36. GPIO implementation
4.37. VIC Primary Interrupt Controller implementation
4.38. SIC implementation
4.39. Primary interrupt controller registers
4.40. Interrupt signals to primary interrupt controller
4.41. Secondary interrupt controller registers
4.42. Interrupt signals to secondary interrupt controller
4.43. KMI implementation
4.44. MBX implementation
4.45. MCI implementation
4.46. MPMC implementation
4.47. SDRAM register values
4.48. PCI controller implementation
4.49. PCI bus memory map for AHB M2 bridge
4.50. PCI controller registers
4.51. PCI_IMAPx register format
4.52. PCI_SELFID register format
4.53. PCI_FLAGS register format
4.54. PCI_SMAPx register format
4.55. PCI backplane configuration header addresses (self-config)
4.56. PCI backplane configuration header addresses (normal configuration)
4.57. PCI configuration space header
4.58. PCI bus commands supported
4.59. RTC implementation
4.60. Serial bus implementation
4.61. Serial bus register
4.62. Serial bus device addresses
4.63. SCI implementation
4.64. SSP implementation
4.65. SSMC implementation
4.66. Register values for Intel flash, standard async read mode, no bursts
4.67. Register values for Intel flash, async page mode
4.68. Register values for Samsung SRAM
4.69. Register values for Spansion BDS640
4.70. Register values for Spansion LV256
4.71. System controller implementation
4.72. Timer implementation
4.73. UART implementation
4.74. USB implementation
4.75. USB controller base address
4.76. VFP9 implementation
4.77. Watchdog implementation
A.1. SSP signal assignment
A.2. Smartcard connector signal assignment
A.3. Signals on expansion connector
A.4. Serial plug signal assignment
A.5. Multimedia Card interface signals
A.6. CLCD Interface board connector J18
A.7. VGA connector signals
A.8. Mouse and keyboard port signal descriptions
A.9. Ethernet signals
A.10. HDRX (J9) signals
A.11. HDRY (J12) signals
A.12. HDRZ (J8) signals
A.13. Test point functions
A.14. Trace connector J14
A.15. AHB monitor connector J17
A.16. FPGA debug connector J39
B.1. PB926EJ-S electrical characteristics
B.2. Current requirements from DC IN (12V)
B.3. Current requirements from J34
B.4. Maximum current load on supply voltage rails
B.5. ARM926EJ-S PXP Development Chip bus timing
B.6. ARM926EJ-S PXP Development Chip memory timing
B.7. Peripherals and controller timing
C.1. Displays available with adaptor board
C.2. Power configuration
C.3. Touchscreen host interface signal assignment
C.4. CLCD interface connector J2
C.5. LCD prototyping connector J1
C.6. Touchscreen prototyping connector J3
C.7. Inverter prototyping connector J4
C.8. A/D and keypad J13
D.1. LED indicators
D.2. Configuration switches
D.3. Power and reset switches
D.4. Test points
D.5. ATX power connector
D.6. Mictor connector pinout
E.1. Memory width encoding
E.2. Chip Select information block
E.3. Example contents of a static memory expansion EEPROM
E.4. Example contents of a dynamic memory expansion EEPROM
E.5. SDR, Single data rate dynamic memory connector signals
E.6. Static memory connector signals
F.1. RealView Logic Tile clock signals
G.1. Reset behavior register names and values
G.2. Device property register names and values

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The PB926EJ-S generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision ANovember 2003First release.
Revision BApril 2004Second release. Added configuration details for USB debug, PCI, and Boot Monitor.
Revision CNovember 2005Third release. Corrected reported defects and added requested enhancements.
Revision DAugust 2006Fourth release. Corrected reported defects and added requested enhancements.
Revision EMay 2007Fifth release. Corrected reported defects and added requested enhancements.
Revision FOctober 2007Sixth release. Corrected reported defect.
Revision GApril 2008Seventh release. Corrected reported defect.
Revision HMarch 2009Eighth release. Corrected reported defect.
Revision IJuly 2010Ninth release. Document update.
Copyright © 2003-2010 ARM Limited. All rights reserved.ARM DUI 0224I
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