The ARM926EJ-S CPU is a member of the ARM9 Thumb^® family. The ARM926EJ-S (r0p3) macrocell is a 32-bit cached processor with ARMv5TE architecture that supports the ARM and Thumb instruction sets and includes features for direct execution of Java byte codes. Executing Java byte codes requires the Java Technology Enabling Kit (JTEK).

The ARM926EJ-S contains a Memory Management Unit (MMU), 32KB data and instruction caches, and 32KB of data and instruction Tightly Coupled Memory (TCM). The TCM operates with a single wait-state and provides higher data rates than external memory.

The ARM926EJ-S processor uses two separate AHB masters for instructions and data to maximize system speed. The DMA controller has two AHB masters. The CLCD controller has one AHB master.

There are also two expansion master buses (AHB M1 and AHB M2) and one expansion slave bus (AHB S). The expansion bus bridges are configurable to support different performance and complexity trade-offs.

The bus matrix inside the ARM926PXP development chip manages the multiple paths between each master and the peripherals and memory. The matrix enables different bus masters to access peripherals.

The Embedded Trace Macrocell (ETM) provides signals for off-chip trace. The ETM transmits a 4, 8, or 16-bit packet to an external trace port analyzer where the signals can be stored and later analyzed to reconstruct the code flow.

This high-performance, low-power Vector Floating-Point (VFP) coprocessor implements the VFPv2 vector floating-point architecture.

The MOVE coprocessor is a video encoding accelerator designed to accelerate Motion Estimation (ME) algorithms within block-based video encoding schemes such as MPEG4 and H.263. For more information on the MOVE coprocessor, see the ARM MOVE Coprocessor Technical Reference Manual. (The MOVE documentation is only available to licensees of this product.)

This high-performance graphic accelerator operates on 3D scene data (as batches of triangles) sent from the main processor. Triangles are written directly to a tile accelerator so that the CPU is not stalled during processing. For more information on the MBX coprocessor, see the ARM MBX HR-S Graphics Core Technical Reference Manual. (The MBX documentation is only available to licences of this product.)

The ARM926PXP development chip contains deskew PLL that uses an external reference clock to generate internal clocks for the CPU, AHB bus, memory, and off-chip peripherals. Dividers in the chip are programmable and give considerable flexibility in clock rates for the CPU, bridges, and memory.

The ARM926PXP development chip includes a multi-port memory controller (for dynamic memory) and a static memory controller. Both controllers have 32-bit interfaces to external memory. See Memory interface.

The PrimeCell DMAC enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. See DMA.

The PrimeCell VIC provides an interface to the interrupt system and provides vectored interrupt support for high-priority interrupt sources from:

See Interrupts.

The CLCDC provides a flexible display interface that supports a VGA monitor and color LCD displays. See CLCDC interface.

The UARTs perform serial-to-parallel conversion on data received from a peripheral device and parallel-to-serial conversion on data transmitted to the peripheral device. See UART interface.

There are four 32-bit down counters that can be used to generate interrupts at programmable intervals. A Watchdog module can be used to trigger a system reset in the event of software failure. A Real-Time-Clock is fed with an external 1Hz signal.

The SSP provides a master or slave interface for synchronous serial communications using Motorola SPI, TI, or National Semiconductor Microwire devices.

The Smart Card interface signals are programmable to enable support for a Smart Card, Security Identity Module (SIM) card, or similar module.

A Watchdog module can be used to trigger an interrupt or system reset in the event of software failure.