Versatile Application Baseboard for ARM926EJ-S User Guide: 4.6. Direct Memory Access Controller

4.6. Direct Memory Access Controller

The PrimeCell Direct Memory Access Controller (DMAC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. The DMAC is located in the ARM926PXP development chip.

Table 4.27. DMAC implementation

Property	Value
Location	ARM926PXP development chip
Memory base address	`0x10130000` for DMAC (PL010)
Interrupt	17 on the primary controller
DMA	NA
Release version	ARM DMAC PL080 r1p0
Reference documentation	ARM PrimeCell DMA (PL080) Technical Reference Manual (see also DMA)

Sixteen peripheral DMA interfaces are provided by the PrimeCell DMAC, of which ten are used by the ARM926PXP development chip peripherals (UART0-3, SCI, and SSP) and three are made available for devices in the FPGA.

Note

The DMA controller cannot access the Tightly Coupled Memory in the ARM926EJ-S core. Other access limitations are:

DMAC master 0 can always access the DMA APB and FPGA peripherals
DMAC master 1 can always access dynamic and static memory and FPGA peripherals.
Accesses to other regions are usually mapped to AHB M2.

See AHB bridges and the bus matrix.

Table 4.28 shows the DMA channel allocation.

Table 4.28. DMA channels

DMA channel	DMA Requester
15	UART0 Tx
14	UART0 Rx
13	UART1 Tx
12	UART1 Rx
11	UART2 Tx
10	UART2 Rx
9	SSP Tx
8	SSP Rx
7	SCI Tx
6	SCI Rx
5	Reserved
4	Reserved
3	Reserved
2	MCI (device in the FPGA)
1	AACI TX (device in the FPGA)
0	AACI RX (device in the FPGA)

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