Versatile Application Baseboard for ARM926EJ-S User Guide: 3.4.2. ICS307 programmable clock generators

3.4.2. ICS307 programmable clock generators

Two programmable (6-200 MHz) clocks are supplied to the FPGA by the programmable MicroClock ICS307 clock generators (OSC0 and OSC1):

OSC0: Reference clock for XTALCLKEXT. This is normally used as the external AHB clock and the reference for the PLL that generates CPUCLK inside the ARM926PXP development chip.
OSC1: This the reference for the CLCD controller (a buffered version of this clock is output to the ARM926PXP development chip as CLCDCLKEXT.

OSC0 uses a 24MHz crystal as its reference and outputs a fixed-frequency 24MHz signal (REFOUT) and a programmble frequency (XCLKEXT). The 24MHz REFOUT clock from OSC0 is used as a reference signal for:

The reference divider input for programmable oscillator OSC1.
the Ethernet controller clock (the Ethernet serial data clock is generated from a 25MHz crystal on the Ethernet controller).
the USB controller clock
the external clock on the expansion connector
the external peripheral clocks for the SCI, UART, and SSP in the ARM926PXP development chip.
the input to divide-by-24 logic in the PLD that produces the 1MHz reference clock for the timers.

The output frequencies of the ICS307s are controlled by divider values loaded into the serial data input pins on the oscillators. The divider values are defined by the SYS_OSC0 and SYS_OSC1 registers. The register format for the divider values is shown in Figure 3.17.

Figure 3.17. SYS_OSCx register format

Note

Bit 23 is loaded into the shift register first and bit 0 is loaded last. Data is clocked into the ICS307DATA pins of the oscillators on the rising edge of ICS307CLK. One of the ICS307STRB[4:0] signals is pulsed HIGH to latch the serial data into the divider control register.

You can calculate the oscillator output frequency from the formula:

where:

VDW

Is the VCO divider word (4 - 511) from SYS_OSCx[8:0]

RDW

Is the reference divider word (1 - 127) from SYS_OSCx[15:9]

DIVIDE

Is the divide ratio (2 to 10) selected from SYS_OSCx[18:16]:

b000 selects divide by 10
b001 selects divide by 2
b010 selects divide by 8
b011 selects divide by 4
b100 selects divide by 5
b101 selects divide by 7
b110 selects divide by 3
b111 selects divide by 6.

For more information on the ICS clock generator and a frequency calculator, see the ICS web site at www.icst.com. For details of the clock control registers, see Status and system control registers.

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