The major components on the platform are:
ARM926PXP development chip equipped with:
ARM926EJ-S processor that supports 32-bit ARM and 16-bit Thumb instructions sets and includes features for direct execution of Java byte codes. Executing Java byte codes requires the Java Technology Enabling Kit (JTEK)
Tightly-Coupled Memory (TCM) for code (32KB) and data (32KB)
cache memory for code (32KB) and data (32KB)
Memory Management Unit (MMU)
Multi-layer bus matrix that enables simultaneous transfers from several bus masters.
MOVE™ Graphics coprocessor
MBX graphics accelerator
Multi-Port Memory Controller (MPMC) for direct connection to dynamic memory
Synchronous Static Memory Controller (SSMC) for direct connection to static memory
VFP9 Vector Floating Point coprocessor
AHB bridge that provides access to peripherals outside the development chip (such as those in the FPGA)
system controller
DMA controller
Vectored Interrupt Controller (VIC)
Color LCD controller
Three UARTs
Synchronous Serial Port (SSP)
Smart Card Interface (SCI)
Two eight-bit GPIOs (another GPIO is dedicated to board status signals)
Real Time Clock (RTC)
Two programmable timers
Watchdog timer
Embedded Trace Macrocell (ETM9)
Embedded-ICE logic for JTAG debugging
Phase-Locked Loop (PLL)
configuration block.
Field Programmable Gate-Array (FPGA) that implements:
MMC/SD card MCI controller
two KMI controllers for keyboard and mouse
interface to onboard Ethernet controllers
interface to onboard audio CODEC
interface to onboard real-time clock
interface to onboard audio CODEC
interface to EEPROM on memory expansion boards
registers for status, ID, onboard switches, LEDs, and clock control
a secondary interrupt controller and external DMA control logic.
128MB of 32-bit wide SDRAM
2MB of 32-bit wide static RAM
64MB of 32-bit wide NOR flash
64MB of 16-bit wide NAND Disk-on-Chip flash
programmable clock generators
expansion connectors for UARTs
expansion connectors on AB-IB1 for CLCD, UARTs, GPIO, and static memory
debug and test connectors for JTAG and Trace port
DIP switches and LEDs
power conversion circuitry
time of year clock with backup battery.
Figure 1.3 shows the architecture of the Versatile/AB926EJ-S. Most of the peripherals are part of the ARM926PXP development chip. The internal peripherals and controllers are connected to a bus matrix that manage the bus routing. Additional peripherals are implemented in the FPGA. The FPGA connects to the AHB M2 bus on the ARM926PXP development chip.
Note
The Versatile/AB926EJ-S is a compact version of the Versatile/PB926EJ-S. Some of the functionality of the Versatile/PB926EJ-S is not present in the Versatile/AB926EJ-S and missing signals or registers are listed where relevant to simplify moving code between the two products. See the Versatile Platform Baseboard for ARM926EJ-S User Guide for more information on the Versatile/AB926EJ-S. See Differences between the Versatile/PB926EJ-S and Versatile/AB926EJ-S for a summary of the differences in between the development boards.
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