HBI-0118
Copyright © 2004-2011 ARM Limited. All rights reserved.
Table of Contents
- Preface
- 1. Introduction
- 2. Getting Started
- 2.1. Setting up the Versatile/AB926EJ-S
- 2.2. Selecting the boot memory type
- 2.3. Connecting JTAG debugging equipment
- 2.4. Connecting the Trace Port Analyzer
- 2.5. Supplying power
- 2.6. Using the Versatile/AB926EJ-S Boot Monitor
- 2.6.1. Running the Boot Monitor
- 2.6.2. Rebuilding the Boot Monitor
- 2.6.3. Loading Boot Monitor into NOR flash
- 2.6.4. Loading Boot Monitor into Disk-on-Chip
- 2.6.5. Using the Disk-on-Chip configure utility program
- 2.6.6. Redirecting character output to hardware devices
- 2.6.7. Rebuilding the platform library
- 2.6.8. Building an application with the platform library
- 2.6.9. Loading and running an application from NOR flash
- 2.6.10. Running an image from Disk-on-Chip
- 2.6.11. Using a boot script to run an image automatically
- 3. Hardware Description
- 3.1. ARM926PXP development chip
- 3.2. FPGA
- 3.3. Reset controller
- 3.4. Clock architecture
- 3.5. Advanced Audio Codec Interface, AACI
- 3.6. CLCDC interface
- 3.7. DMA
- 3.8. Ethernet interface
- 3.9. GPIO interface
- 3.10. Interrupts
- 3.11. Keyboard/Mouse Interface, KMI
- 3.12. SD/MultiMedia Card Interface, MCI
- 3.13. Serial bus interface
- 3.14. Smart card interface, SCI
- 3.15. Synchronous Serial Port, SSP
- 3.16. User switches and LEDs
- 3.17. USB interface
- 3.18. UART interface
- 3.19. Test, configuration, and debug interfaces
- 4. Programmer’s Reference
- 4.1. Memory map
- 4.2. Configuration and initialization
- 4.3. Status and system control registers
- 4.3.1. ID Register, SYS_ID
- 4.3.2. Switch Register, SW
- 4.3.3. LED Register, SYS_LED
- 4.3.4. Oscillator registers, SYS_OSCx
- 4.3.5. Lock Register, SYS_LOCK
- 4.3.6. 100Hz Counter, SYS_100HZ
- 4.3.7. Flag registers, SYS_FLAGx and SYS_NVFLAGx
- 4.3.8. Reset Control Register, SYS_RESETCTL
- 4.3.9. MCI Register, SYS_MCI
- 4.3.10. Flash Control Register, SYS_FLASH
- 4.3.11. CLCD Control Register, SYS_CLCD
- 4.3.12. 24MHz Counter, SYS_24MHZ
- 4.3.13. Miscellaneous System Control Register, SYS_MISC
- 4.3.14. Oscillator test registers, SYS_TEST_OSC0
- 4.4. Advanced Audio CODEC Interface, AACI
- 4.5. Color LCD Controller, CLCDC
- 4.6. Direct Memory Access Controller
- 4.7. Ethernet
- 4.8. General Purpose Input/Output, GPIO
- 4.9. Interrupt controllers
- 4.10. Keyboard and Mouse Interface, KMI
- 4.11. MBX
- 4.12. MultiMedia Card Interface, MCI
- 4.13. MOVE video coprocessor
- 4.14. MultiPort Memory Controller, MPMC
- 4.15. Real Time Clock, RTC
- 4.16. Smart Card Interface, SCI
- 4.17. Synchronous Serial Port, SSP
- 4.18. Synchronous Static Memory Controller, SSMC
- 4.19. Serial bus interface
- 4.20. System Controller
- 4.21. Timers
- 4.22. UART
- 4.23. USB interface
- 4.24. Vector Floating Point, VFP9
- 4.25. Watchdog
- A. Signal Descriptions
- A.1. Audio CODEC interface
- A.2. Ethernet interface
- A.3. Peripheral expansion connector
- A.4. Static memory expansion connector
- A.5. Keyboard and mouse interface
- A.6. MMC and SD flash card interface
- A.7. Smart card interface
- A.8. UART interface
- A.9. USB interface
- A.10. VGA display interface
- A.11. Battery connector
- A.12. Test and debug connections
- B. Specifications
- C. Versatile/AB-IB1 Interface Board
- D. Versatile/AB-IB2 Interface Board
- E. LCD Kits
- F. Static Memory Expansion Board
- G. Configuring a USB Debug Connection
List of Figures
- 1.1. Versatile/AB926EJ-S layout (top)
- 1.2. Versatile/AB926EJ-S layout (bottom)
- 1.3. Versatile/AB926EJ-S block diagram
- 2.1. Location of configuration switches
- 2.2. JTAG connection
- 2.3. USB debug port connection
- 2.4. Example of MultiTrace and JTAG connection
- 2.5. Example of RealView-ICE and RealView Trace
- 2.6. Power connector J23
- 3.1. ARM926PXP development chip block diagram
- 3.2. Multiple masters
- 3.3. AHB map
- 3.4. Core APB and DMA APB map
- 3.5. Memory devices
- 3.6. FPGA block diagram
- 3.7. FPGA reload sequence
- 3.8. FPGA configuration
- 3.9. Reset logic
- 3.10. Boot memory remap logic
- 3.11. Reset signal sequence
- 3.12. Programmable reset level
- 3.13. Power-on reset and configuration timing
- 3.14. Standby switch and power-supply control
- 3.15. Clock distribution
- 3.16. ARM926PXP development chip internal clock logic
- 3.17. SYS_OSCx register format
- 3.18. Audio interface
- 3.19. Display interface
- 3.20. DMA channels
- 3.21. Ethernet interface architecture
- 3.22. GPIO block diagram
- 3.23. External and internal interrupt sources
- 3.24. KMI block diagram
- 3.25. MMC interface
- 3.26. Serial bus block diagram
- 3.27. SCI block diagram
- 3.28. SSP block diagram
- 3.29. Switch and LED interface
- 3.30. OTG243 block diagram
- 3.31. UARTs block diagram
- 3.32. JTAG connector, CFGEN link, and LED
- 3.33. JTAG connector signals
- 3.34. JTAG signal routing
- 4.1. AHB Data bus memory map
- 4.2. Booting from Disk on Chip
- 4.3. Booting from NOR flash
- 4.4. ID Register, SYS_ID
- 4.5. SYS_SW
- 4.6. SYS_LED
- 4.7. Oscillator Register, SYS_OSCx
- 4.8. Lock Register, SYS_LOCK
- 4.9. SYS_RESETCTL
- 4.10. SYS_MCI
- 4.11. SYS_CLCD
- 4.12. SYS_MISC
- 4.13. AACI ID register
- 4.14. Secondary interrupt registers
- A.1. Audio connectors
- A.2. Ethernet connector J4
- A.3. KMI connector J7
- A.4. MMC/SD card socket J6 pin numbering
- A.5. MMC card
- A.6. Smartcard contacts assignment
- A.7. Serial connector J8
- A.8. OTG socket J5
- A.9. VGA connector J1
- A.10. Battery connector
- A.11. Test points and debug connectors
- A.12. Switches and LEDs
- A.13. Multi-ICE JTAG connector J21
- A.14. USB debug connector J19
- A.15. Mictor connector J12
- B.1. Versatile/AB926EJ-S mechanical details
- C.1. Versatile/AB-IB1 mechanical details
- C.2. Installing the Versatile/AB-IB1
- C.3. Serial connector
- C.4. CLCD Interface connector J3
- C.5. SSP expansion interface J7
- C.6. GPIO connector J8
- C.7. Samtec connector J6
- D.1. AB-IB2 block diagram
- D.2. AB-IB2 layout
- D.3. Installing the IB2
- D.4. CLCD block diagram
- D.5. Samtec connector J6
- D.6. Keyboard module
- D.7. Keyboard block diagram
- D.8. Prototyping area block diagram
- D.9. GSM block diagram
- E.1. Small CLCD enclosure
- E.2. Large CLCD enclosure
- E.3. 3.8 display mounted directly onto top of adaptor board.
- E.4. CLCD adaptor board connection
- E.5. CLCD buffer and power supply control links
- E.6. Touchscreen and keypad interface
- E.7. Touchscreen resistive elements
- E.8. CLCD adaptor board mechanical layout
- F.1. Static memory board block diagram
- F.2. Memory board installation
- F.3. Chip select information block
- F.4. Samtec connectors
- F.5. Static memory board layout
- G.1. Nodes added to Connection Control window
- G.2. The Connection Control window
- G.3. ARM926PXP development chip detected
- G.4. Error shown when unpowered devices are detected
- G.5. Error shown when no devices are detected
- G.6. Error shown when the USB debug port is not functioning
- G.7. Connection Properties window
- G.8. The Debug tab of the Register pane
List of Tables
- 2.1. Selecting the boot device
- 2.2. Selecting the FPGA image
- 2.3. Boot Monitor commands
- 2.4. Boot Monitor Configure commands
- 2.5. Boot Monitor NOR flash commands
- 2.6. Boot Monitor Debug commands
- 2.7. Configure utility commands
- 3.1. Configuration switch S4
- 3.2. FPGA image selection
- 3.3. Reset sources and effects
- 3.4. Reset signal descriptions
- 3.5. Versatile/AB926EJ-S clocks and clock control signals
- 3.6. Audio system specification
- 3.7. Display interface signals
- 3.8. DMA signals for external devices
- 3.9. Ethernet signals
- 3.10. MMC/SD interface signals
- 3.11. MMC signals
- 3.12. Serial bus addresses
- 3.13. Serial bus signals
- 3.14. Smart Card interface signals
- 3.15. SSP signal descriptions
- 3.16. USB interface signal assignment
- 3.17. Serial interface signal assignment
- 3.18. JTAG related signals
- 4.1. Memory map
- 4.2. Peripherals not present on Versatile/AB926EJ-S
- 4.3. System registers
- 4.4. Primary interrupt mapping
- 4.5. Secondary interrupt mapping
- 4.6. DMA functionality
- 4.7. Selecting the boot device
- 4.8. Memory chip selects and address range
- 4.9. Register map for system control registers
- 4.10. ID Register, SYS_ID bit assignment
- 4.11. Oscillator Register, SYS_OSCx bit assignment
- 4.12. Lock Register, SYS_LOCK bit assignment
- 4.13. Flag registers
- 4.14. Reset level control
- 4.15. MCI control
- 4.16. Flash control
- 4.17. SYS_CLCD register
- 4.18. SYS_MISC
- 4.19. Oscillator test registers
- 4.20. AACI implementation
- 4.21. Modified AACI PeriphID3 register
- 4.22. CLCDC implementation
- 4.23. PrimeCell CLCDC register differences
- 4.24. Values for different display resolutions
- 4.25. Assignment of display memory to R[7:0], G[7:0], and B[7:0]
- 4.26. PL110 hardware playback mode
- 4.27. DMAC implementation
- 4.28. DMA channels
- 4.29. Ethernet implementation
- 4.30. GPIO implementation
- 4.31. VIC Primary Interrupt Controller implementation
- 4.32. SIC implementation
- 4.33. Primary interrupt controller registers
- 4.34. Interrupt signals to primary interrupt controller
- 4.35. Secondary interrupt controller registers
- 4.36. Interrupt signals to secondary interrupt controller
- 4.37. KMI implementation
- 4.38. MBX implementation
- 4.39. MCI implementation
- 4.40. MPMC implementation
- 4.41. SDRAM register values
- 4.42. RTC implementation
- 4.43. SCI implementation
- 4.44. SSP implementation
- 4.45. SSMC implementation
- 4.46. Serial bus implementation
- 4.47. Serial bus register
- 4.48. Serial bus device addresses
- 4.49. System controller implementation
- 4.50. Timer implementation
- 4.51. UART implementation
- 4.52. USB implementation
- 4.53. USB controller base address
- 4.54. VFP9 implementation
- 4.55. Watchdog implementation
- A.1. Ethernet signals
- A.2. Peripheral expansion connector J25/J26
- A.3. Static memory connector J1/4
- A.4. Mouse and keyboard port signal descriptions
- A.5. Multimedia Card interface signals
- A.6. Smartcard connector signal assignment
- A.7. Serial plug signal assignment
- A.8. VGA connector signals
- A.9. Test point functions
- A.10. Links
- A.11. Trace signals
- B.1. Versatile/AB926EJ-S electrical characteristics
- B.2. Current requirements from DC IN (12V)
- B.3. Maximum current load on supply voltage rails
- B.4. Maximum clock rates
- C.1. Serial plug signal assignment
- C.2. CLCD adaptor board connector J3
- C.3. SSP signal assignment
- D.1. Memory map
- D.2. Control register
- D.3. Status register
- D.4. Interrupt status register
- D.5. Interrupt enable register
- D.6. Keyboard data register
- D.7. CLCD module signals
- D.8. Values for the QVGA TFT display
- D.9. Camera module connector J3
- D.10. Camera module reverse function
- D.11. Camera signals
- D.12. Keyboard coding
- D.13. Keyboard module connector
- D.14. Prototyping area signals
- D.15. GSM connector signals
- E.1. Displays available with adaptor board
- E.2. Values for different TFT resolutions
- E.3. Power configuration
- E.4. Touchscreen host interface signal assignment
- E.5. CLCD interface connector J2
- E.6. LCD prototyping connector J1
- E.7. Touchscreen prototyping connector J3
- E.8. Inverter prototyping connector J4
- E.9. A/D and keypad J13
- F.1. Memory width encoding
- F.2. Chip Select information block
- F.3. Example contents of a static memory expansion EEPROM
- F.4. Static memory connector signals
- G.1. Reset behavior register names and values
- G.2. Device property register names and values
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.
Unrestricted Access is an ARM internal classification.
Federal Communications Commission Notice
The Versatile/AB926EJ-S, Versatile/AB-IB1, and Versatile/IB-2 are test equipment and consequently are exempt from part 15 of the FCC Rules under section 15.103 (c).
The Versatile/AB-IB2 contains an Enfora Enabler II-G GSM Radio Module (FCC ID: MIVGSM0108). The GSM module complies with Part 15 of the FCC Rules for equipment intended for use in a commercial, industrial, or business environment. Use of the GSM module present on the Versatile/AB-IB2 is subject to the following conditions:
This GSM module must not cause harmful interference.
This GSM module must accept any interference received, including interference that may cause undesired operation.
The Versatile/AB926EJ-S and the Versatile/AB-IB2 must be used as a mobile or fixed device as defined under FCC regulations. Do not operate the Versatile/AB926EJ-S and the Versatile/AB-IB2 as a portable device. Use of the device on a desktop or other applications where the antenna can easily be relocated are considered by the FCC to be mobile applications.
Antenna gain for the GSM module output is limited to 3dBi. Modifications and/or additions to the Enfora Enabler II-G GSM transceiver, including use of antennas with higher than 3dBi gain, are prohibited. Mobile devices are limited to 2W EIRP under Part 24.
The nominal RF output power of the GSM transceiver is 1.0W. The antenna supplied with the Versatile/AB-IB2 has a gain of 0dBi. The requirement for less than 2W EIRP will therefore be met if there are no modifications to the transceiver or antenna.
Enfora certifies that its Enfora Enabler II-G GSM Radio Module complies with the RF hazard requirements applicable to broadband PCS equipment operating under the authority of 47 CPR Part 24, Subpart E of the FCC Rules and Regulations. This certification is contingent upon installation, operation, and use of the Enfora Enabler II-G GSM Module in accordance with all instructions provided to the OEM and the end user. When installed and operated in a manner consistent with the instructions provided, the Enfora Enabler II-G meets the maximum permissible exposure (MPE) limits for general population/uncontrolled exposure as defined in Section 1.1310 of the FCC Rules and Regulations.
Warning
The AB-IB2 GSM module emits RF radiation. Keep at least 20cm (7.9in) separation distance from the antenna and the human body.
Follow all safety instructions in this manual, any warning
notices on the product, and any applicable legal requirements and
safety regulations (see also GSM module and the Enfora Enabler IIG GSM/GPRS
Radio Modem Integration Guide GSM0108-01 at the Enfora
website at www.enfora.com.)
The transmitter and antenna must not be collocated or operating in conjunction with any other antenna or transmitter. Failure to observe this warning could produce an RF exposure condition.
CE Declaration of Conformity
The system should be powered down when not in use.
The board generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:
ensure attached cables do not lie across the card
reorient the receiving antenna
increase the distance between the equipment and the receiver
connect the equipment into an outlet on a circuit different from that to which the receiver is connected
consult the dealer or an experienced radio/TV technician for help
Note
It is recommended that wherever possible Shielded interface cables be used.
| Revision History | ||
|---|---|---|
| Revision A | December 2004 | First release |
| Revision B | July 2006 | Second release with fixes for errata |
| Revision C | March 2009 | Third release with fixes for errata |
| Revision D | April 2011 | Fourth release with fixes for errata |
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