6.7.7. FLD and FST

Floating-point load and store.


FLD<precision>{cond} Fd, [Rn{, #offset}]
FST<precision>{cond} Fd, [Rn{, #offset}]
FLD<precision>{cond} Fd, label
FST<precision>{cond} Fd, label



must be either S for single-precision, or D for double-precision.


is an optional condition code (see VFP and condition codes).


is the VFP register to be loaded or saved. The precision of Fd must match the precision specified in <precision>.


is the ARM register holding the base address for the transfer.


is an optional numeric expression. It must evaluate to a numeric constant at assembly time. The value must be a multiple of 4, and lie in the range –1020 to +1020. The value is added to the base address to form the address used for the transfer.


is a program-relative expression. See Register-relative and program-relative expressions for more information.

label must be within ±1KB of the current instruction.


The FLD instruction loads a floating-point register from memory. The FST instruction saves the contents of a floating-point register to memory.

One word is transferred if <precision> is S. Two words are transferred if <precision> is D.

There is also an FLD pseudo-instruction (see FLD pseudo-instruction).


    FLDD    d5, [r7, #-12]
    FLDSNE  s3, [r2, #72+count]
    FSTS    s2, [r5]
    FLDD    d2, [r15, #addr-{PC}]
    FLDS    s9, fpconst
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