RealView® Developer Kit Assembler Guide Chapter 4. ARM Instruction Reference

Chapter 4. ARM Instruction Reference

This chapter describes the ARM^® instructions that are supported by the ARM assembler. It contains the following sections:

See to Table 4.1 to locate individual instructions and pseudo-instructions.

Table 4.1. Location of ARM instructions

Mnemonic	Brief description	Page	Architecture^[1]
`ADC`, `ADD`	Add with carry, Add	ADD, SUB, RSB, ADC, SBC, and RSC	All
`ADR` pseudo-instruction	Load program-relative or register-relative address (short range)	ADR ARM pseudo-instruction	All
`ADRL` pseudo-instruction	Load program-relative or register-relative address into a register (medium range)	ADRL ARM pseudo-instruction	All
`AND`	Logical AND	AND, ORR, EOR, and BIC	All
`B`	Branch	B and BL	All
`BIC`	Bit clear	AND, ORR, EOR, and BIC	All
`BKPT`	Breakpoint	BKPT	5
`BL`	Branch with link	B and BL	All
`BLX`	Branch, link and exchange	BLX	5T^[2]
`BX`	Branch and exchange	BX	4T^b
`CDP`, `CDP2`	Coprocessor data operation	CDP, CDP2	2, 5
`CLZ`	Count leading zeroes	CLZ	5
`CMN`, `CMP`	Compare negative, Compare	CMP and CMN	All
`CPS`	Change processor state	CPS	6
`CPY`	Copy	MOV, CPY and MVN	6
`EOR`	Exclusive OR	AND, ORR, EOR, and BIC	All
`LDC`, `LDC2`	Load coprocessor	LDC, STC	2, 5
`LDM`	Load multiple registers	LDM and STM	All
`LDR`	Load register	ARM Memory access instructions	All
`LDR` pseudo-instruction	Load register pseudo-instruction	ARM pseudo-instructions	All
`LDREX`	Load register exclusive	LDREX and STREX	6
`MAR`	Move from registers to 40-bit accumulator	MAR, MRA	XScale^[3]
`MCR`, `MCR2`, `MCRR`, `MCRR2`	Move from register(s) to coprocessor	MCR, MCR2, MCRR, and MCRR2	2, 5, 5E^[4], 6
`MIA`, `MIAPH`, `MIAxy`	Multiply with internal 40-bit accumulate	MIA, MIAPH, and MIAxy	XScale
`MLA`	Multiply accumulate	MUL and MLA	2
`MOV`	Move	MOV, CPY and MVN	All
`MRA`	Move from 40-bit accumulator to registers	MAR, MRA	XScale
`MRC`, `MRC2`	Move from coprocessor to register	MRC, MRC2	2, 5
`MRRC`, `MRRC2`	Move from coprocessor to 2 registers	MRRC and MRRC2	5E^d, 6
`MRS`	Move from PSR to register	MRS	3
`MSR`	Move from register to PSR	MSR	3
`MUL`	Multiply	MUL and MLA	2
`MVN`	Move not	MOV, CPY and MVN	All
`NOP` pseudo-instruction	Generates the preferred no-operation code.	NOP ARM pseudo-instruction	All
`ORR`	Logical OR	AND, ORR, EOR, and BIC	All
`PKHBT`, `PKHTB`	Pack halfwords	PKHBT and PKHTB	6
`PLD`	Cache preload	PLD	5E^d
`QADD`, `QDADD`, `QDSUB`, `QSUB`	Saturating arithmetic	QADD, QSUB, QDADD, and QDSUB	5ExP^[5]
`QADD8`, `QADD16`, `QADDSUBX`, `QSUB8`, `QSUB16`, `QSUBADDX`	Byte-wise and halfword-wise parallel signed saturating arithmetic	Parallel add and subtract	6
`REV`, `REV16`, `REVSH`	Reverse byte order	REV, REV16, and REVSH	6
`RFE`	Return from exception	RFE	6
`RSB`, `RSC`, `SBC`	Reverse sub, Reverse sub with carry, Sub with carry	ADD, SUB, RSB, ADC, SBC, and RSC	All
`SADD8`, `SADD16`, `SADDSUBX`	Byte-wise and halfword-wise parallel signed arithmetic	Parallel add and subtract	6
`SADD8TO16`, `SADD8TO32`, `SADD16TO32`	Sign extend and add	SADD_TO_ and UADD_TO_	6
`SEL`	Select bytes according to CPSR GE flags	SEL	6
`SETEND`	Set endianness for memory accesses	SETEND	6
`SHADD8`, `SHADD16`, `SHADDSUBX`, `SHSUB8`, `SHSUB16`, `SHSUBADDX`	Byte-wise and halfword-wise parallel signed halving arithmetic	Parallel add and subtract	6
`SMLAD`	Dual signed multiply-accumulate (32 <= 32 + 16 x 16 + 16 x 16)	SMLAD and SMLSD	6
`SMLAL`	Signed multiply-accumulate (64 <= 64 + 32 x 32)	UMULL, UMLAL, SMULL and SMLAL	M^[6]
`SMLALD`	Dual signed multiply-accumulate long (64 <= 64 + 16 x 16 + 16 x 16)	SMLALD and SMLSLD	6
`SMLALxy`	Signed multiply-accumulate (64 <= 64 + 16 x 16)	SMLALxy	5ExP^e
`SMLAWy`	Signed multiply-accumulate (32 <= 32 + 32 x 16)	SMLAWy	5ExP^e
`SMLAxy`	Signed multiply-accumulate (32 <= 32 + 16 x 16)	SMLAxy	5ExP^e
`SMLSD`	Dual signed multiply-subtract-accumulate (32 <= 32 + 16 x 16 – 16 x 16)	SMLAD and SMLSD	6
`SMLSLD`	Dual signed multiply-subtract-accumulate long (64 <= 64 + 16 x 16 – 16 x 16)	SMLALD and SMLSLD	6
`SMULL`	Signed multiply (64 <= 32 x 32)	UMULL, UMLAL, SMULL and SMLAL	M^f
`SMULWy`	Signed multiply (32 <= 32 x 16)	SMULWy	5ExP^e
`SMULxy`	Signed multiply (32 <= 16 x 16)	SMULxy	5ExP^e
`SMMLA`	Signed top word multiply-accumulate (32 <= 32 + TopWord(32 x 32))	SMMLA and SMMLS	6
`SMMLS`	Signed top word multiply-subtract (32 <= 32 – TopWord(32 x 32))	SMMLA and SMMLS	6
`SMMUL`	Signed top word multiply (32 <= TopWord(32 x 32))	SMMUL	6
`SMUAD`, `SMUSD`	Dual signed multiply, and add or subtract products	SMUAD and SMUSD	6
`SRS`	Store return state	SRS	6
`SSAT`	Signed saturate	SSAT and USAT	6
`SSAT16`	Signed saturate, parallel halfwords	SSAT16 and USAT16	6
`SSUB8`, `SSUB16`, `SSUBADDX`	Byte-wise and halfword-wise parallel signed arithmetic	Parallel add and subtract	6
`STC`, `STC2`	Store coprocessor	LDC, STC	2, 5ExP^e
`STM`	Store multiple registers	LDM and STM	All
`STR`	Store register	ARM Memory access instructions	All
`STREX`	Store register exclusive	LDREX and STREX	6
`SUB`	Subtract	ADD, SUB, RSB, ADC, SBC, and RSC	All
`SUNPK`	Signed unpack	SUNPK and UUNPK	6
`SWI`	Software interrupt	SWI	All
`SWP`	Swap registers and memory	SWP and SWPB	3
`TEQ`, `TST`	Test equivalence, Test	TST and TEQ	All
`UADD8`, `UADD16`, `UADDSUBX`	Byte-wise and halfword-wise parallel unsigned arithmetic	Parallel add and subtract	6
`UADD8TO16`, `UADD8TO32`, `UADD16TO32`	Zero extend and add	SADD_TO_ and UADD_TO_	6
`UHADD8`, `UHADD16`, `UHADDSUBX`, `UHSUB8`, `UHSUB16`, `UHSUBADDX`	Byte-wise and halfword-wise parallel unsigned halving arithmetic	Parallel add and subtract	6
`UMAAL`	Unsigned multiply accumulate accumulate long (64 <= 32 + 32 + 32 x 32)	UMAAL	6
`UMLAL`, `UMULL`	Unsigned multiply-accumulate, multiply (64 <= 32 x 32 + 64), (64 <= 32 x 32)	UMULL, UMLAL, SMULL and SMLAL	M^f
`UQADD8`, `UQADD16`, `UQADDSUBX`, `UQSUB8`, `UQSUB16`, `UQSUBADDX`	Byte-wise and halfword-wise parallel unsigned saturating arithmetic	Parallel add and subtract	6
`USAD8`	Unsigned sum of absolute differences	USAD8 and USADA8	6
`USADA8`	Accumulate unsigned sum of absolute differences	USAD8 and USADA8	6
`USAT`	Unsigned saturate	SSAT and USAT	6
`USAT16`	Unsigned saturate, parallel halfwords	SSAT16 and USAT16	6
`USUB8`, `USUB16`, `USUBADDX`	Byte-wise and halfword-wise parallel unsigned arithmetic	Parallel add and subtract	6
`UUNPK`	Unsigned unpack	SUNPK and UUNPK	6
^[1]`n` : available in architecture version `n` and above ^[2]`n`T : available in T variants of architecture version `n` and above ^[3]XScale: XScale coprocessor instructions ^[4]`5`E : available in ARMv5E, except ExP variants, and ARMv6 and above ^[5]`5`ExP : available in ARMv5E, including ExP variants, and ARMv6 and above ^[6]M : available in ARMv3M, and ARMv4 and above, except xM versions

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