RealView ® Developer Kit AssemblerGuide

Version 1.0


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback
Feedback on RealView Developer Kit
Feedback on this book
1. Introduction
1.1. About the RVCT assemblers
2. Writing ARM and Thumb Assembly Language
2.1. Introduction
2.1.1. Code examples
2.2. Overview of the ARM architecture
2.2.1. Architecture versions
2.2.2. ARM and Thumb state
2.2.3. Processor mode
2.2.4. Registers
2.2.5. ARM instruction set overview
2.2.6. ARM instruction capabilities
2.2.7. Thumb instruction setoverview
2.2.8. Thumb instruction capabilities
2.2.9. Differences between Thumb and ARM instruction sets
2.3. Structure of assembly language modules
2.3.1. Layout of assembly language source files
2.3.2. An example ARM assembly language module
2.3.3. Calling subroutines
2.3.4. An example Thumb assembly languagemodule
2.4. Using the C preprocessor
2.5. Conditional execution
2.5.1. The ALU status flags
2.5.2. Execution conditions
2.5.3. Using conditional execution in ARMstate
2.5.4. Example of the use of conditional execution
2.6. Loading constants into registers
2.6.1. Direct loading withMOV and MVN
2.6.2. Loading with LDR Rd, =const
2.6.3. Loading floating-point constants
2.7. Loading addresses into registers
2.7.1. Direct loading with ADR and ADRL
2.7.2. Loading addresses withLDR Rd, = label
2.8. Load and store multiple register instructions
2.8.1. ARM LDM and STM instructions
2.8.2. LDM and STM addressing modes
2.8.3. Implementing stackswith LDM and STM
2.8.4. Block copy with LDMand STM
2.8.5. Thumb LDM and STM instructions
2.9. Using macros
2.9.1. Test-and-branch macro example
2.9.2. Unsigned integer division macro example
2.10. Describing data structures with MAPand FIELD directives
2.10.1. Relative maps
2.10.2. Register-based maps
2.10.3. Program-relative maps
2.10.4. Finding the end of the allocated data
2.10.5. Forcing correct alignment
2.10.6. Using register-based MAP and FIELDdirectives
2.10.7. Using two register-based structures
2.10.8. Avoiding problems withMAP and FIELD directives
2.11. Using frame directives
3. Assembler Reference
3.1. Command syntax
3.2. Format of source lines
3.3. Predefined register and coprocessornames
3.3.1. Predeclared register names
3.3.2. Predeclared program status register names
3.3.3. Predeclared floating-point register names
3.3.4. Predeclared coprocessor names
3.4. Built-in variables
3.4.1. Determining the armasm version atassembly time
3.5. Symbols
3.5.1. Symbol naming rules
3.5.2. Variables
3.5.3. Numeric constants
3.5.4. Assembly time substitutionof variables
3.5.5. Labels
3.5.6. Local labels
3.6. Expressions, literals, and operators
3.6.1. String expressions
3.6.2. String literals
3.6.3. Numeric expressions
3.6.4. Numeric literals
3.6.5. Floating-point literals
3.6.6. Register-relative andprogram-relative expressions
3.6.7. Logical expressions
3.6.8. Logical literals
3.6.9. Operator precedence
3.6.10. Unary operators
3.6.11. Binary operators
4. ARM Instruction Reference
4.1. Conditional execution
4.1.1. The Q flag
4.2. ARM Memory access instructions
4.2.1. LDR and STR, wordsand unsigned bytes
4.2.2. LDR and STR, halfwordsand signed bytes
4.2.3. LDR and STR, doublewords
4.2.4. LDM and STM
4.2.5. PLD
4.2.6. SRS
4.2.7. RFE
4.2.8. LDREX and STREX
4.2.9. SWP and SWPB
4.3. ARM general data processing instructions
4.3.1. Flexible second operand
4.3.2. ADD, SUB, RSB, ADC,SBC, and RSC
4.3.3. AND, ORR, EOR, andBIC
4.3.4. MOV, CPY and MVN
4.3.5. CMP and CMN
4.3.6. TST and TEQ
4.3.7. CLZ
4.3.8. SEL
4.3.9. REV, REV16, and REVSH
4.4. ARM multiply instructions
4.4.1. MUL and MLA
4.4.2. UMULL, UMLAL, SMULLand SMLAL
4.4.3. SMULxy
4.4.4. SMLAxy
4.4.5. SMULWy
4.4.6. SMLAWy
4.4.7. SMLALxy
4.4.8. SMUAD and SMUSD
4.4.9. SMMUL
4.4.10. SMLAD and SMLSD
4.4.11. SMMLA and SMMLS
4.4.12. SMLALD and SMLSLD
4.4.13. UMAAL
4.4.14. MIA, MIAPH, and MIAxy
4.5. ARM saturating instructions
4.5.1. What saturating means
4.5.2. QADD, QSUB, QDADD,and QDSUB
4.5.3. SSAT and USAT
4.6. ARM parallel instructions
4.6.1. Parallel add and subtract
4.6.2. USAD8 and USADA8
4.6.3. SSAT16 and USAT16
4.7. ARM packing and unpacking instructions
4.7.1. SUNPK and UUNPK
4.7.2. SADD_TO_ and UADD_TO_
4.7.3. PKHBT and PKHTB
4.8. ARM branch instructions
4.8.1. B and BL
4.8.2. BX
4.8.3. BLX
4.8.4. BXJ
4.9. Coprocessor instructions
4.9.1. CDP, CDP2
4.9.2. MCR, MCR2, MCRR, andMCRR2
4.9.3. MRC, MRC2
4.9.4. MRRC and MRRC2
4.9.5. LDC, STC
4.9.6. LDC2, STC2
4.10. Miscellaneous ARM instructions
4.10.1. SWI
4.10.2. MRS
4.10.3. MSR
4.10.4. CPS
4.10.5. SETEND
4.10.6. BKPT
4.10.7. MAR, MRA
4.11. ARM pseudo-instructions
4.11.1. ADR ARM pseudo-instruction
4.11.2. ADRL ARM pseudo-instruction
4.11.3. LDR ARM pseudo-instruction
4.11.4. SEXT and UEXT ARM pseudo-instructions
4.11.5. NOP ARM pseudo-instruction
5. Thumb Instruction Reference
5.1. Thumb memory access instructions
5.1.1. LDR and STR, immediateoffset
5.1.2. LDR and STR, registeroffset
5.1.3. LDR and STR, pc orsp relative
5.1.4. PUSH and POP
5.1.5. LDMIA and STMIA
5.2. Thumb arithmetic instructions
5.2.1. ADD and SUB, low registers
5.2.2. ADD, high or low registers
5.2.3. ADD and SUB, sp
5.2.4. ADD, pc or sp relative
5.2.5. ADC, SBC, and MUL
5.3. Thumb general data processing instructions
5.3.1. AND, ORR, EOR, andBIC
5.3.2. ASR, LSL, LSR, andROR
5.3.3. CMP and CMN
5.3.4. MOV and CPY
5.3.5. MVN and NEG
5.3.6. TST
5.3.7. REV, REV16, and REVSH
5.3.8. SEXT and UEXT
5.4. Thumb branch instructions
5.4.1. B
5.4.2. BL
5.4.3. BX
5.4.4. BLX
5.5. Thumb miscellaneous instructions
5.5.1. SWI
5.5.2. CPS
5.5.3. SETEND
5.5.4. BKPT
5.6. Thumb pseudo-instructions
5.6.1. ADR Thumb pseudo-instruction
5.6.2. LDR Thumb pseudo-instruction
5.6.3. NOP Thumb pseudo-instruction
6. Vector Floating-point Programming
6.1. The vector floating-point coprocessor
6.1.1. VFP architectures
6.2. Floating-point registers
6.2.1. Register banks
6.2.2. Vectors
6.3. Vector and scalar operations
6.3.1. Control of scalar, vector and mixed operations
6.4. VFP and condition codes
6.5. VFP system registers
6.5.1. FPSCR, the floating-point status andcontrol register
6.5.2. FPEXC, the floating-pointexception register
6.5.3. FPSID, the floating-point system IDregister
6.5.4. Modifying individual bits of a VFPsystem register
6.6. Flush-to-zero mode
6.6.1. When to use flush-to-zero mode
6.6.2. The effects of using flush-to-zero mode
6.6.3. Operations not affected by flush-to-zeromode
6.7. VFP instructions
6.7.1. FABS, FCPY, and FNEG
6.7.2. FADD and FSUB
6.7.3. FCMP
6.7.4. FCVTDS
6.7.5. FCVTSD
6.7.6. FDIV
6.7.7. FLD and FST
6.7.8. FLDM and FSTM
6.7.9. FMAC, FNMAC, FMSC,and FNMSC
6.7.10. FMDRR and FMRRD
6.7.11. FMDHR, FMDLR, FMRDH,and FMRDL
6.7.12. FMRS and FMSR
6.7.13. FMRRS and FMSRR
6.7.14. FMRX, FMXR, and FMSTAT
6.7.15. FMUL and FNMUL
6.7.16. FSITO and FUITO
6.7.17. FSQRT
6.7.18. FTOSI and FTOUI
6.8. VFP pseudo-instruction
6.8.1. FLD pseudo-instruction
6.9. VFP directives andvector notation
6.9.1. VFPASSERT SCALAR
6.9.2. VFPASSERT VECTOR
7. Directives Reference
7.1. Alphabetical list of directives
7.2. Symbol definition directives
7.2.1. GBLA, GBLL, and GBLS
7.2.2. LCLA, LCLL, and LCLS
7.2.3. SETA, SETL, and SETS
7.2.4. RLIST
7.2.5. CN
7.2.6. CP
7.2.7. DN and SN
7.2.8. FN
7.3. Data definition directives
7.3.1. LTORG
7.3.2. MAP
7.3.3. FIELD
7.3.4. SPACE
7.3.5. DCB
7.3.6. DCD and DCDU
7.3.7. DCDO
7.3.8. DCFD and DCFDU
7.3.9. DCFS and DCFSU
7.3.10. DCI
7.3.11. DCQ and DCQU
7.3.12. DCW and DCWU
7.3.13. DATA
7.4. Assembly control directives
7.4.1. Nesting directives
7.4.2. MACRO and MEND
7.4.3. MEXIT
7.4.4. IF, ELSE, ENDIF, andELIF
7.4.5. WHILE and WEND
7.5. Frame description directives
7.5.1. FRAME ADDRESS
7.5.2. FRAME POP
7.5.3. FRAME PUSH
7.5.4. FRAME REGISTER
7.5.5. FRAME RESTORE
7.5.6. FRAME RETURN ADDRESS
7.5.7. FRAME SAVE
7.5.8. FRAME STATE REMEMBER
7.5.9. FRAME STATE RESTORE
7.5.10. FUNCTION or PROC
7.5.11. ENDFUNC or ENDP
7.6. Reporting directives
7.6.1. ASSERT
7.6.2. INFO
7.6.3. OPT
7.6.4. TTL and SUBT
7.7. Miscellaneous directives
7.7.1. ALIGN
7.7.2. AREA
7.7.3. CODE16 and CODE32
7.7.4. END
7.7.5. ENTRY
7.7.6. EQU
7.7.7. EXPORT or GLOBAL
7.7.8. EXPORTAS
7.7.9. EXTERN
7.7.10. GET or INCLUDE
7.7.11. GLOBAL
7.7.12. IMPORT
7.7.13. INCBIN
7.7.14. INCLUDE
7.7.15. KEEP
7.7.16. NOFP
7.7.17. REQUIRE
7.7.18. REQUIRE8 and PRESERVE8
7.7.19. RN
7.7.20. ROUT
Glossary

List of Figures

4.1. ROR
4.2. RRX
6.1. VFP register banks

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A May 2003 Release for RVDK v1.0
Revision B March2004 Release for RVDK v1.0.1
Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM DUI 0231B
Non-Confidential