Note

Except for the clock and JTAG signals, the Core Tile has the same signal on both the upper and lower pins. Some of the upper and lower HDRZ signals can be isolated (see Control of AHB data bus and HDRZ signals).

Most of the pins on the RealView Logic Tiles have different signals on the upper and lower Logic Tile HDRZ pins. If the upper signal on the Logic Tile is named ZUn and the lower signal is named ZLn, the table entry is Zxn. Replace x by L for the signal on the lower header and by U for the signal on the upper header. For example, the pin 1 signal for the lower connector is ZL128 and the pin 1 signal for the upper connector is ZU128.