Note

Except for the clock, JTAG, and MEMEXPB[21:0] signals, the Core Tile has the same signal on both the upper and lower pins. Some of the upper and lower HDRZ signals can also be isolated from each other (see Isolation and foldover of header signals).

Most of the pins on the RealView Logic Tiles have different signals on the upper and lower Logic Tile HDRZ pins. If the upper signal on the Logic Tile is named ZUn and the lower signal is named ZLn, the table entry is Zxn. Replace x by L for the signal on the lower header and by U for the signal on the upper header.

For example, the pin 1 signal for the Logic Tile lower connector is ZL128 and the pin 1 signal for the upper connector is ZU128. The corresponding signals for the Core Tile are MEMEXPB0 (upper) and ZL128 (lower).

If the upper signal on a tile has a completely different name than the lower signal, both names are listed and the signal on the upper connector is indicated by a (U) and the signal on the lower connector is indicated by a (L).