6.5.2. Timing parameter tables

Table 6.16 shows the clock and reset timing parameters.

Table 6.16. Clock and reset parameters

TclkHCLK clock period30
TisrstHRESETn deasserted setup time before HCLK15

Table 6.17 shows the AHB slave input parameters.

Table 6.17. AHB slave input parameters

TistrTransfer type setup time before HCLK5
TisaHADDR[31:0] setup time before HCLK10
TisctlHWRITE, HSIZE[2:0] and HBURST[2:0] setup time before HCLK5
TiswdWrite data setup time before HCLK5
TisrdyReady setup time before HCLK5

Table 6.18 shows the AHB slave output parameters.

Table 6.18. AHB slave output parameters

TovrspResponse valid time after HCLK15
TovrdData valid time after HCLK15
TovrdyReady valid time after HCLK15

Table 6.19 shows the bus master input parameters.

Table 6.19. Bus master input timing parameters

TisgntHGRANTx setup time before HCLK5
TisrdyReady setup time before HCLK5
TisrspResponse setup time before HCLK5
TisrdRead data setup time before HCLK5

Table 6.20 shows the bus master output timing parameters.

Table 6.20. Bus master output timing parameters

TovtrTransfer type valid time after HCLK15
TovaAddress valid time after HCLK15
TovctlHWRITE, HSIZE[2:0] and HBURST[2:0] valid time after HCLK15
TovwdWrite data valid time after HCLK15
TovreqRequest valid time after HCLK15
TovlckLock valid time after HCLK15

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