4.2. Clocks

Clock related signals for the CT926EJ-S are shown in Figure 4.1.

Figure 4.1. Clock signals

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The ARM926EJ-S test chip on the Core Tile accepts or generates the following clocks:


A reference clock to the test chip clock dividers. This is the source for the PLL incorporated into the test chip. The PLL generates the core clock CLK that is used internally in the test chip.


the core clock (this is internal to the test chip). The frequency of CLK is controlled by a PLL within the test chip.

The internal PLL can be bypassed by setting PLLBYPASS HIGH. This sets CLK to the same frequency as the reference clock and allows you to model implementations where the core does not have a PLL.


The test chip produces the HCLK signal by dividing CLK by a value of between 1 and 8 as determined by HCLKDIV[2:0]. The divider can be effectively bypassed by setting a divide by value of 1. The HCLK signal is distributed by the test chip on five identical signals:

  • HCLKEXT0 can be selected for CLK_NEG_UP_OUT

  • HCLKEXT1 can be selected for CLK_NEG_DN_OUT

  • HCLKEXT2 is output on the upper header as X_HCLK_UP

  • HCLKEXT3 is output on the lower header as X_HCLK_DN

  • HCLKEXT4 can be selected for CLK_GLOBAL.

See Clocks and the ARM926EJ-S Technical Reference Manual for details of the Core Tile clock signals.

The core clock frequency for the CT926EJ-S is calculated from:

CLK = (REFCLK/(PLLREFDIV[3:0]+1) * (PLLFBDIV[7:0]+1)) / (PLLOUTDIV[2:0]+1)

That is:

137kHz < REFCLK/PLLRFDIV[3:0] + 1 < 275MHz

55MHz < CLK < 275MHz


The ARM926EJ-S test chip does not use the HCLKIN signal. The test chip HCLK is always generated internally based on the REFCLK input and the dividers.

The ARM926EJ-S Core Tile has a manufacturing test block that, if enabled, changes the clock division ratios and disables the interrupt request signals. The test block can be disabled by writing 0x0 to the USERIN bits of the SYS_CONFIGDATA1 register on the Emulation Baseboard. The block can also be disabled by using a FPGA image in the baseboard that drives the USERIN[3] signal LOW.

If the PLLBYPASS signal is HIGH, the core uses the external clock instead of the internal PLL. (This signal is typically LOW.)

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