3.6.1. Data read/write control for AHB data

Interconnection between HDATA[31:0], HRDATA[31:0], and HWDATA[31:0] is selected by control signals DATACTL[2:0] from the Core Tile HDRZ. Figure 3.8 shows an example of a Logic Tile controlling the data bus switches. The typical data bus modes are listed in Table 3.6.

See Core Tile PLD signals for a description of the PLD interface.

Table 3.6. Data bus switch function

DATACTL[2:0]ConnectionDescription
b111NoneMultiplexed read and write data bus in test chip (on HRDATA) and from Logic Tile. The HDATA bus is not used on either the Core Tile or Logic Tile.
b110HDATA to HWDATASeparate read (HRDATA) and write (HWDATA) data buses in test chip and from Logic Tile
bx00HDATA to HWDATA, HRDATA to HWDATASeparate read and write data buses from Logic Tile are combined to connect to single multiplexed data bus (either HRDATA or HWDATA) on test chip
b011HRDATA to HWDATASeparate read and write data buses in test chip and multiplexed HRDATA bus from Logic Tile. The HDATA bus is not used on either the Core Tile or Logic Tile.

Figure 3.8. Read/write control

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If the DATACTLx signal is LOW, the corresponding switches are closed.

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