3.7.1. Core Tile PLD signals

The PLD on the Core Tile performs the following functions:

The PLD is controlled by the serial interface signals listed in Table 3.7. These signals typically connect to an attached Logic Tile or IM-LT3 Interface Module. The FPGA in the external tile contains registers that hold the values to send to the PLD and received values from the PLD. The FPGA also provides the serialization and deserialization logic required for the PLD interface.

Note

The images for the Logic Tile FPGA and Core Tile PLD depend on the combination of boards that are in the stack. The application notes include FPGA and PLD images.

Table 3.7. PLD control signals

SignalDescription
PLDCLKClocks data into or out of the PLD
PLDD1Serial data input to PLD
PLDD0Serial data output from PLD
PLDRESETnReset selects mode for PLD (LOW is startup, HIGH is runtime configuration)

The Core Tile PLD manages the Core Tile configuration and status signals listed in Table 3.8

Table 3.8. PLD configuration signals

SignalDirectionFunction
ZCTL[3:0]PLD outputZ Through control, see Through/Break control for HDRZ.
CLKSEL[4:0]PLD outputClock selection, see Clocks.
DACnCS[2:0]PLD outputChip select to DAC.
DAC_DIN[2:0]PLD outputData to DAC, see Setting the VDDCORE voltage.
ADC_nCS[1:0]PLD outputChip select to ADC.
ADC_CLK[1:0]PLD inputClock for data from ADC.
ADC_SSTRB[1:0]PLD inputStrobe for ADC. Indicates that a conversion has finished.
ADC_DOUT[1:0]PLD inputData from ADC, see Reading the voltages and currents.
PGOODPLD inputPower good indication from power supply regulators, see PGOOD signal.
DMEMSIZE[2:0]PLD outputTest chip data TCM configuration, see Memory located inside test chip.
IMEMSIZE[2:0]PLD outputTest chip instruction TCM configuration, see Memory located inside test chip.
MAN_ID[3:0]PLD inputBoard identification from resistor links. This is set at manufacture and identifies the board build.
PWR_nSHDN[2:0]PLD outputShutdown to the Vdd core power supplies, see Power supply control.

PLD function at power on

At power-on-reset, a controller in an external tile sends a configuration sequence to the PLD on the Core Tile as shown in Figure 3.10. The PLD control signals are described in Table 3.7. nSYSRST is an external signal from an attached motherboard.

Figure 3.10. Power on signals to the Core Tile PLD

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Table 3.9 lists the configuration and status signals that are received by or transmitted from the PLD at power on (after nSYSPOR goes HIGH).

Table 3.9. Power-on configuration signals by clock cycle

ClockPLDD1PLDD0Description
-LOWLOWNo activity while nSYSPOR is LOW
0LOWLOWFirst rising edge of clock after nSYSPOR goes HIGH
1ZCTL[3]MANID[3]ZCTL data is clocked into the PLD and the state of the MANID links is clocked out of the PLD.
2ZCTL[2]MANID[2]
3ZCTL[1]MANID[1]
4ZCTL[0]MANID[0]
5CLKSEL[5]PLDID[3]CLKSEL multiplexor data is clocked into the PLD and the internal PLD ID is clocked out.
6CLKSEL[4]PLDID[2]
7CLKSEL[3]PLDID[1]
8CLKSEL[2]PLDID[0]
9CLKSEL[1]PGOOD
10CLKSEL[0]-
11DMEMSIZE[2]-The requested size for the TCM/cache data memory is clocked into the PLD.
12DMEMSIZE[1]-
13DMEMSIZE[0]-
14IMEMSIZE[2]-The requested size for the TCM/cache instruction memory is clocked into the PLD.
15IMEMSIZE[1]-
16IMEMSIZE[0]-
17LOWLOWNo further activity until nSYSRST goes HIGH

PLD function after power on

After the power-on configuration finishes, the PLD is inactive until the nSYSRST signal goes HIGH. If nSYSRST is HIGH, The PLD continuously receives DAC packets from the serial interface and transmits ADC packets to the serial interface as shown in Figure 3.11.

Figure 3.11. ADC and DAC data stream

ADC and DAC data stream

Note

After nSYSRST goes HIGH, the ADC and DAC data packets repeat continuously.

The format of the ADC packet is shown in Figure 3.12.

Figure 3.12. ADC packet format

ADC packet format

The format of the DAC packet is shown in Figure 3.13.

Figure 3.13. DAC packet format

DAC packet format

Table 3.10 lists the PLD input and output signals after nSYSPOR goes HIGH.

Table 3.10. Run configuration signals by clock cycle

ClockPLDD1 (PLD input)PLDD0 (PLD output)Description
-LOWLOWNo activity while nSYSPOR is LOW
0DACSELA[2]ADCSELB[2]

First cycle after nSYSPOR goes HIGH. The DACSEL signals select which DAC value is transmitted in the current packet.

The value of the ADCSEL signals indicate the ADC value that is transmitted in the current packet.

1DACSELA[1]ADCSELA[2]
2DACSELA[0]ADCSELB[1]
3LOWADCSELA[1]
4DACDIN[7]ADCSELB[0]Start of DAC data.
5DACDIN[6]ADCSELA[0]-
6DACDIN[5]LOW-
7DACDIN[4]LOW-
8DACDIN[3]LOW-
9DACDIN[2]LOW-
10DACDIN[1]LOW-
11DACDIN[0]LOW-
12PWR_nSHDN[2]LOWShutdown settings for power supply are clocked into the PLD.
13PWR_nSHDN[1]LOW-
14PWR_nSHDN[0]LOW-
15LOWLOW-
16DACSELA[2]HIGHSecond DAC packet starts with DAC selection bits.
17DACSELA[1]HIGH
18DACSELA[0]LOW-
19LOWLOW-
20DACDIN[7]ADC_DOUTB[11]ADC data starts. DAC data starts.
21DACDIN[6]ADC_DOUTA[11]-
22DACDIN[5]ADC_DOUTB[10]-
23DACDIN[4]ADC_DOUTA[10]-
24DACDIN[3]ADC_DOUTB[9]-
25DACDIN[2]ADC_DOUTA[9]-
26DACDIN[1]ADC_DOUTB[8]-
27DACDIN[0]ADC_DOUTA[8]-
28PWR_nSHDN[2]ADC_DOUTB[7]Shutdown settings for power supply are clocked into the PLD.
29PWR_nSHDN[1]ADC_DOUTA[7]
30PWR_nSHDN[0]ADC_DOUTB[6] 
31LOWADC_DOUTA[6] 
32DACSELA[2]ADC_DOUTB[5]Third DAC packet starts.
33DACSELA[1]ADC_DOUTA[5]-
34DACSELA[0]ADC_DOUTB[4]-
35LOWADC_DOUTA[4]-
36DACDIN[7]ADC_DOUTB[3]Start of DAC data
37DACDIN[6]ADC_DOUTA[3]-
38DACDIN[5]ADC_DOUTB[2]-
39DACDIN[4]ADC_DOUTA[2]-
40DACDIN[3]ADC_DOUTB[1]-
41DACDIN[2]ADC_DOUTA[1]-
42DACDIN[1]ADC_DOUTB[0]-
43DACDIN[0]ADC_DOUTA[0]End of ADC data. End of DAC packet.
44PWR_nSHDN[2]LOWShutdown settings for power supply are clocked into the PLD.
45PWR_nSHDN[1]LOW
46PWR_nSHDN[0]LOW
47LOWLOW-
48DACSELA[2]LOWFourth DAC packet starts.
49DACSELA[1]PGOODPower good signal is clocked out of PLD. End of ADC packet.
50DACSELA[0]LOW-

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