5.2.1. Test chip clock control

During a power-on reset the value on the HRDATA[31:0] pins is loaded into the test chip PLL configuration register. The value comes from the attached Logic Tile FPGA image and typically sets:

The core clock frequency can be set from the clock control logic on the external Logic Tile. The ARM1136JF-S test chip does not use the HCLK DIV functions implemented on other Core Tiles. For details of the clock selection and routing logic that is inside the test chip, see the ARM1136JF-S Technical Reference Manual.

Note

If the PLLBYPASS signal is HIGH, the core uses the external clock instead of the internal PLL. (This signal is typically LOW.)

Figure 5.1. Clock selection

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The clocks generated by the clock and reset generator are controlled by the Clock Generator Control Register at 0x3F200080. Table 5.1 lists the format of the Clock Generator Control Register.

Table 5.1. Clock Generator Control Register

BitDescription
[31]Reserved, should be zero
[30]

Value of HSYNCENIRW and SYNCENIRW when the port is configured as asynchronous:

0 = HSYNCENIRW and SYNCENIRW signals are driven to 0

1 = HSYNCENIRW and SYNCENIRW signals are driven to 1.

[29]

Value of HSYNCENPD and SYNCENPD when the port is configured as synchronous:

0 = HSYNCENPD and SYNCENPD signals are driven to 0

1 = HSYNCENPD and SYNCENPD signals are driven to 1.

[28]

Selects the clock source for HCLKI and HCLKE:

0 = HCLKI and HCLKE derived from PLLCLK

1 = HCLKI and HCLKE derived from HCLKIN.

[27]

Configures Instruction, Data Read, and Data Write ports of the ARM1136JF-S test chip as synchronous or asynchronous:

If Bit 27 is set to 0 the ports are configured as synchronous:

HCLKIRW is driven from CLK

HCLKIRWEN is driven from HCLKIEN

HSYNCENIRW and SYNCENIRW are driven to 1.

If Bit 27 is set to 1 the ports are configured as asynchronous:

HCLKIRW is driven from HCLKI

HCLKIRWEN is driven to 1

HCLKIRW is driven from HCLKI

HSYNCENIRW and SYNCENIRW are driven from bit 30 of this register.

[26]

Configures whether Peripheral and DMA ports of the ARM1136JF-S processor are configured as synchronous or asynchronous:

If Bit 26 is set to 0 the ports are configured as synchronous:

HCLKPD is driven from CLK

HCLKPDEN is driven from HCLKIEN

HSYNCENPD and SYNCENPD are driven to 1

If Bit 26 is set to 1 the ports are configured as asynchronous:

HCLKPD is driven from HCLKI

HCLKPDEN is driven to 1

HSYNCENPD and SYNCENPD are driven from bit 30 of this register.

[25:20]Sets the clock ratio for the HCLKE domain.
[19:14]Sets the clock ratio for the HCLKI domain.
[13:8]Sets the clock ratio for the CLK domain.
[7:0]Reserved, should be zero

The programmed clock ratios determine the divisor between the source clock and the output clock. The source clock for CLK is always PLLCLK (the signal PLLBYPASS must be LOW). The divisor selected is given by the following equation:

Divisor = Programmed ratio +1

The maximum divisor that you can program is 63.

Not all values of the Clock Generator Control Register are legal. The following restrictions apply:

  1. HCLKE ratio must be an integer multiple of the HCLKI.

  2. If you program the ports to be synchronous, that is if bit 27 is 0 and bit 26 is 0, you must program the CLK ratio to be 1:1.

  3. If you select the clock source for HCLKI and HCLKE from HCLKIN (bit 28 is set to 1), then you must program the ports to be asynchronous (set bits 27 and 26 to 1). You must also set the HCLKI ratio must be 1:1.

Caution

Changes to bits [28:26] of this register only take effect during reset (ARM_nRESET is LOW). The changes to the clock ratios can take place at any point. You must exercise care to ensure that the programming of bits [28:26] have propagated to the clock generator before selecting an asynchronous ratio. This means that the sequence for programming an asynchronous clock ratio involves setting bits [27:26], forcing a simple reset, and then programming the asynchronous clock ratio.

The clocks are disabled if ARM_nPORESET is LOW.

Changing any of the clock ratio values only takes effect during a reset. This is because clock ratio values are propagated from the register to the clock dividers during a reset only. This reset might be the same reset used to propagate changes in the asynchronous control bits, bits[28:26].

The minimum duration of an externally applied reset on the signal ARM_nRESET is one clock cycle of the slowest clock.

The Clock Divisor Register is accessed using the AHBPCAPT block.

The reset values of the Clock Generator Control Register are defined from the Configuration Register, see Table 5.22.

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