3.5.3. Reading the voltages and currents

The ADCs on the Core Tile continuously read the voltages and currents and update registers in the PLD, see PLD function after power on. The PLD transmits these values over the serial interface to the FPGA in the attached Logic Tile.

The LSB of the ADC reading corresponds to 1.221 mV. (Two times the 2.5V VREF of the ADC divided by 4095.) The formula for the VDDCORE, VDDPLL, VDDIO, and voltages is:

VVDD = 1.221mV * VOLTAGE[11:0]

Caution

All voltages except VDDCOREx_DIFF and TP_SENSE are divided by two before being fed to the ADC. The formula for the test point voltage is therefore:

VTP = 2.442mV * VOLTAGE[11:0]

The TP_SENSE voltage should not exceed 2.5V for accurate readings and must not exceed 3.3V to prevent damage to the converters.

Voltages proportional to the ARM_VDDCORE[6:1] currents are developed across the sense resistors (see Figure 3.7). Each of the sense resistors has a voltage amplifier because the sense voltage is too low to measure directly with the ADC. To calculate the current through an ARM_VDDCOREx line:

IARM_VDDCOREx = Vref * VOLTAGE[11:0] / (RSENSE * GAIN * (212-1))

Figure 3.7. Voltage divider and current sense circuit

Voltage divider and current sense circuit

Note

By default, all of the RSENSE resistors are 0Ω . It is not therefore possible to measure the current. You can replace the existing sense resistors with new ones of, for example, 1Ω.

If you change the sense resistors, adjust the core voltage to compensate for the voltage drop, for example, a 1Ω sense resistor drops 0.1V at 100mA. The default GAIN is 22, so a 1Ω sense resistor with 100mA current results in an ADC voltage input of 2.2V.

PGOOD signal

The power-good signal (PGOOD) to the PLD is pulled LOW if one of the VDDCOREA, VDDCOREA, VDDCOREA, or VDDIO output voltages is not within 7.5% of its selected value.

The VDDCOREA, VDDCOREA and VDDCOREA voltages can be measured by the ADC if the voltage outputs are connected to one of the VDDCOREx_CURRENT lines. Setting the VDDCORE voltages is described in Setting the VDDCORE voltage.

The ARM_VDDIO voltage is measured by the ARM_VDDIO_SENSE signal to the ADC. The ARM_VDDIO voltage is fixed at manufacture by the values of resistors R122, R129, and R179 (for the CT926EJ-S, these are 30kΩ, 11kΩ, and 15kΩ) and is given by:

ARM_VDDIO = 0.8V * ( 1 + R122/R129 + R122/R179) = 4.58V

Note

If link R123 is fitted, the ARM_VDDIO supply is connected directly to the 3.3V.

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