3.5.2. Setting the VDDCORE voltage

The core voltages depend on:

The output voltages are given by:

VDDCOREA = 0.8V * (1 + R63/R74 + R63/R176) - CT_VOLTAGEx[7:0]*R63*(IDAC/255)
VDDCOREB = 0.8V * (1 + R89/R94 + R89/R177) - CT_VOLTAGEx[7:0]*R89*(IDAC/255)
VDDCOREC = 0.8V * (1 + R106/R113 +R106/R178) - CT_VOLTAGEx[7:0]*R106*(IDAC/255)

where:

IDAC

The full-range DAC output current (50…A)

CT_VOLTAGEx[7:0]

The eight-bit data value loaded into the PLD from the Logic Tile FPGA. There are two DACs that drive the programmable regulators for VDDCOREA and VDDCOREB.

Resistor values

Refer to the BOM for the resistor values fitted to the Core Tile. The resistor values depend on the test chip fitted and the build variant. The resistor values are typically chosen to give a 0.5V adjustment range for the core voltage. The default value loaded into the DAC is 0x80. A value of 0xFF gives maximum negative offset from the default (-0.25V) and a value of 0x0 gives maximum positive offset from the default (+0.25V).

Figure 3.6. Programmable regulators

Programmable regulators

Shutdown of the VDDCORE regulators

The programmable regulators have can be individually shutdown by the PWR_nSHDN[2:0] signals from the PLD:

  • if PWR_nSHDN[0] is LOW, the VDDCOREA regulator is shut off.

  • if PWR_nSHDN[1] is LOW, the VDDCOREB regulator is shut off.

  • if PWR_nSHDN[2] is LOW, the VDDCOREC regulator is shut off.

See Core Tile PLD signals for a description of the PLD interface.

Copyright © 2004-2011 ARM Limited. All rights reserved.ARM DUI 0273G
Non-ConfidentialID060911