2.4. Using the Core Tile with a custom baseboard

If you are designing a custom baseboard to accept a Core Tile, you must ensure that your board meets the following requirements:

Mechanical layout

The mechanical layout is described in Appendix B Specifications.

Power supplies

The Core Tile uses a 3.3V and 5V supplies to generate local voltages. The test chip core and I/O voltage are controlled by logic in the PLD on the Core Tile. There are resistor links that control the source of the VDDIO voltage (present on HDRX) and the VCCOY voltage (present on HDRY). See the hardware chapters that cover specific Core Tiles for details on the voltage control logic.

Clock control

The primary reference clock must be supplied by an attached Logic Tile or baseboard. The clocking system is described in the hardware chapters that cover specific Core Tiles. There might also be test-chip specific clocking requirements. See the chapters in this manual covering your test chip and the Technical Reference Manual for your core.

JTAG control

The Core Tile does not have a JTAG connector. The baseboard must provide a JTAG connector and route the JTAG signals to the header signals on the Core Tile. JTAG routing is described in Overview of Core Tile configuration and JTAG support.

Bus configuration signals

The processor bus and some of the signals on header HDRZ are controlled through bus switches. Bus configuration is managed by the PLD on the Core Tile, see Overview of Core Tile configuration or Overview of Core Tile configuration.

Memory controller

The Core Tile has two PISMO memory connectors. The memory boards are controlled from external logic (typically from an FPGA on a Logic Tile). If you are using additional memory on the Core Tile, you must implement your own memory controller on your baseboard. The memory interface signals and memory specification is described in Memory expansion connector pinout and Appendix A Static Memory Expansion Board.

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