2.6. Connecting RealView ICE or Multi-ICE

The Core Tile does not have a JTAG connector, but there are JTAG signals present on the header connectors. The Core Tile must be used with an Interface Module or baseboard that contains a JTAG connector. External JTAG equipment can be used to:

Selection between debugging programs and downloading new images to the FPGA is controlled by the CONFIG link that is present on the Interface Module or baseboard. See the documentation supplied with your Interface Module or baseboard for more details on connecting JTAG and connecting the CONFIG link.


Because the Core Tile does not provide nonvolatile memory, programs are lost when the power is removed. Use flash memory for nonvolatile storage. The flash memory can be:

  • Any unused space in the Logic Tile flash. The Logic Tile flash is primarily used for configuration and must contain a valid configuration image for the FPGA.

  • The flash memory on the baseboard.

  • Nonvolatile memory in one of the two PISMO memory expansion slots present on the Core Tile, see Appendix A Static Memory Expansion Board. A memory controller must be implemented in an external Logic Tile to access the Core Tile PISMO expansion memory.

The JTAG connector provides a set of JTAG signals that allow JTAG debugging equipment to be used. If you are debugging a development system with multiple tiles, connect the JTAG debugging equipment to the Interface Module or baseboard and the JTAG signals will be routed through any connected tiles.


Do not use the JTAG connector on the Trace Port Adaptor board. The adapter board must only be used for Trace. Use the JTAG connector on the baseboard or interface module.

The JTAG paths are described in JTAG support and JTAG support.

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