3.4. Clocks

The Core Tile uses reference clocks provided by an attached Logic Tile (or Interface Module) as shown in Figure 3.2.

Figure 3.2. Core Tile clock signals

Core Tile clock signals

Selection of clocks for the Core Tile is done by setting multiplexors as shown in Figure 3.3. Figure 3.3 shows a Core Tile with an ARM926EJ-S test chip. The test chip clock logic and clock control might be different for other test chips.

Figure 3.3. Test chip clock selection (CT926EJ-S)

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Copyright © 2004-2011 ARM Limited. All rights reserved.ARM DUI 0273G