3.4. Clocks

The Core Tile uses reference clocks provided by an attached Logic Tile (or Interface Module) as shown in Figure 3.2.

Figure 3.2. Core Tile clock signals

Core Tile clock signals

Selection of clocks for the Core Tile is done by setting multiplexors as shown in Figure 3.3. Figure 3.3 shows a Core Tile with an ARM926EJ-S test chip. The test chip clock logic and clock control might be different for other test chips.

Figure 3.3. Test chip clock selection (CT926EJ-S)

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