3.8.1. JTAG signals

There are two separate JTAG paths through the Core Tile:

Table 3.12 provides a description of the JTAG signals.


In the description in Table 3.12, the term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan chain. Typically, Multi-ICE or RealView ICE is used, although you can also use hardware from third-party suppliers to debug ARM processors.

Some signals are split in to configuration and debug versions. For example, D_TDO is the data signal for the debug mode chain and C_TDO is the data signal for the configuration mode chain.

Table 3.12. JTAG signal description




nBSTAPENBoundary scan TAP enableIn configuration mode, the boundary scan TAP logic (if present) in a test chip is enabled.


Debug request

(from JTAG equipment)

DBGRQ is a request for the processor core to enter the debug state.


Debug acknowledge

(to JTAG equipment)

DBGACK indicates to the debugger that the processor core has entered debug mode.


FPGA configured

DONE is an open-collector signal that indicates when FPGA configuration is complete. Although this signal is not a JTAG signal, it does affect nSRST. The DONE signal is routed between all FPGAs in the system. The master reset controller on the motherboard senses this signal and holds all the boards in reset (by driving nSRST LOW) until all FPGAs are configured.


Configuration enable

(from jumper on the board at the bottom of the stack)

nCFGEN is an active LOW signal used to put the boards into configuration mode. In configuration mode all FPGAs and PLDs are connected to the scan chain so that they can be configured by the JTAG equipment.


Return TCK enable (from Core Tile to motherboard)

nRTCKEN is an active LOW signal driven by any Core Tile that requires RTCK to be routed back to the JTAG equipment. If nRTCKEN is HIGH, the motherboard drives RTCK LOW. If nRTCKEN is LOW, the motherboard drives the TCK signal back up the stack to the JTAG equipment.


System reset (bidirectional)

nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when a board has been reset by the user.

The open collector nSRST reset signal can be driven LOW by the reset controller on the Core Tile to cause the motherboard to reset the whole system by driving the motherboard signal nSYSRST LOW.

This is also used in configuration mode to control the initialization pin (nINIT) on the FPGAs.

Though not a JTAG signal, nSRST is described because it can be controlled by JTAG equipment.


Test reset (from JTAG equipment)

This active LOW open-collector signal is used to reset the JTAG port and the associated debug circuitry on the processor. It is asserted at power-up by each module, and can be driven by the JTAG equipment. This signal is also used in configuration mode to control the programming pin (nPROG) on FPGAs.


Return TCK

(to JTAG equipment)

Some devices sample TCK (for example a synthesizable core with only one clock), and this has the effect of delaying the time at which a component actually captures data. RTCK is a mechanism for returning the sampled clock to the JTAG equipment, so that the clock is not advanced until the synchronizing device captured the data. In adaptive clocking mode, Multi-ICE is required to wait until it detects an edge on RTCK before changing TCK. In a multiple device JTAG chain, the D_RTCK output from a component connects to the TCK input of the down-stream device. The RTCK signal on the module connectors HDRB returns TCK to the JTAG equipment.


If an Integrator motherboard is present (nMBDET LOW), the RTCK signal to the motherboard is gated with RTCKEN. nRTCKEN is HIGH if there are no synchronizing components in the scan chain the RTCK signal returned from the motherboard is disabled.

D_RTCK is the RTCK signal in the debug scan chain.


Test clock

(from JTAG equipment)

TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good signal integrity. TCK flows up the stack of modules and connects to each JTAG component. However, if there is a device in the scan chain that synchronizes TCK to some other clock, then all down-stream devices are connected to the RTCK signal on that component (see RTCK).

D_TCK is the clock for the debug mode chain and C_TCK is the clock for the configuration mode chain.


Test data in

(from JTAG equipment)

TDI goes up the stack of tiles from the baseboard (or Interface Module) and then back down the stack (as TDO) connecting to each component in the scan chain.

D_TDI is the data signal for the debug mode chain and C_TDI is the data signal for the configuration mode chain.


Test data out

(to JTAG equipment)

TDO is the return path of the data input signal TDI. For a stack of Versatile products, TDI goes up to the top of the stack and returns down as TDO. The JTAG components are connected in the return path so that the length of track driven by the last component in the chain is kept as short as possible.

D_TDO is the data signal for the debug mode chain and C_TDO is the data signal for the configuration mode chain.


Test mode select

(from JTAG equipment)

TMS controls transitions in the tap controller state machine. TMS connects to all JTAG components in the scan chain.

JTAG data and clock logic

Figure 3.14 shows the JTAG clock and data signals.


Single-pole switches are closed if a HIGH signal is present at the control input. Multi-pole switch positions are marked with a 1 for the condition where a HIGH signal is present at the control input.

For Figure 3.14, nCFGEN and nTILEDET are both HIGH indicating normal debug mode and no tile connected above the Core Tile.

Figure 3.14. JTAG clock and data signals

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The clock and data flow in debug and config mode are different. Figure 3.15 and Figure 3.16 show the equivalent flow for each mode. The switches have been replaced by direct connections and the diagram simplified. There is not a tile present above the Core Tile (nTILEDET is pulled HIGH).

Figure 3.15. JTAG data flow in debug mode

JTAG data flow in debug mode

Figure 3.16. JTAG data flow in config mode

JTAG data flow in config mode

JTAG reset and configure logic

Figure 3.17 shows the reset and TMS signals.

Figure 3.17. JTAG reset signals

JTAG reset signals

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