7.2. ARM microprocessor test chip

Table 7.2 provides a brief overview of the signals present on test chips that follow the ARM7 bus specification. The ARM7TDMI test chip, not the ARM7TDMI-S, is normally fitted to the Core Tile. The signals on the schematic and the figures in this chapter use the ARM7TDMI signal names except when the equivalent signal does not exist on the ARM7TDMI. Refer to the ARM7TDMI-S Technical Reference Manual for details on the ARM7TDMI-S.

Note

Different test chips variants might use some of the pins in ways that are specific to that test chip. For more information on signals for particular test chip variants, see the chapter in this manual for the test chip family, the Technical Reference Manual for the test chip, and the information provided on the CD.

Test chip configuration is covered in:

Table 7.2. Test chip signals

GroupARM7TDMI SignalARM7TDMI-S SignalDescription Direction
BusABEMEM64MAddress bus enable, address bus drivers are disabled if this signal is LOWOutput
BusABORTABORTMemory abort or bus errorInput
BusADDR[31:0]ADDR[31:0]Address busOutput
BusALECLKHI

Address latch enable, the address bus, LOCK, MAS[1:0], nRW, nOPC, and nTRANS signals are latched when this signal is held LOW.

Note

This signal is provided for backward compatibility. New designs should use APE.

Output
BusAPE-Address pipeline enable, selects whether the address bus, LOCK, MAS[1:0], nRW, nOPC, and nTRANS signals operate in pipelined (APE HIGH) or depipelined mode (APE LOW) (ARM7TDMI only)Input
BusBL[3:0]-Byte latch control, values on the data bus are latched on the falling edge of MCLK when these signals are HIGH (ARM7TDMI only)Output
BusBC[1:0]SWT_T, LED_NCycle type, versions of MREQ and SEQ that may be modified by F[1:0] (ARM7TDMI-S I/O signals)Output
BusBCETRAMBEEnable BC[1:0] if LOWInput
BusCPACPACoprocessor absentInput
BusCPBCPBCoprocessor busyInput
BusTBITDRAMWE_NThumb instruction set code being executed (ARM7TDMI-S memory control)Output
BusCPSEQCPSEQSequential addressOutput
BusDATA[31:0]DATA[31:0]Data bus (input and output)I/O
BusDBESCANINData bus enable, if HIGH, data appears on the data bus (serial test input for ARM7TDMI-S)Input
BusEABE-External Address Bus Enable, if driven LOW, the A[31:0], nRW, LOCK, nOPC, nTRANS, and MAS[1:0] drivers are put into high impedance state. (ARM7TDMI only)Input
BusEDBEDBEExternal Data Bus Enable, if driven LOW, the D[31:0] drivers are put into high impedance state.Input
BusEEBEINPUT180External Enable, if driven LOW, places external outputs not controlled by EABE or EDBE into high impedance state.Input
BusF[1:0]CFGMEM1, CFGMEM0Cycle function modifiers, these signals can be used to override the requests normally made by the ARM7 processor.Input
BusLOCKLOCKLocked transfer indicationOutput
BusMAS[1:0]SIZE[1:0]Memory access size, indicates to the memory system the size of the data transfer for read and write cycles.Output
BusnCPILCDENCoprocessor instruction (active LOW) (ARM7TDMI-S is I/O signal)Output
BusnENINPOR_NNot enable input, used in conjunction with nENOUT to control the data bus during write cycles.Input
BusnENOUTSCC_NNot enable output, driven LOW before the rising edge of MCLK. Output
BusnM[4:0]RAS0_N, CAS3_N, CAS2_N, CAS1_N, CAS0_NNot processor mode, inverse logic level from the internal status bits that indicate processor operation mode (ARM7TDMI-S CAS[3:0] and RAS[0] are DRAM control signals)Output
BusnMREQCPnMREQMemory request (active LOW)Output
BusnOPCPROT0Opcode fetch (active LOW) Output
BusnRWWRITEData bus directionOutput
BusnTRANSPROT1Not memory translate, LOW if processor is in USER modeOutput
BusnWAITCLKENSystem memory clock enable. If LOW, do not advance the core clock on the next rising CLK input.Input
BusSEL[1:0]CORESYNC, COREFLOWData bus lane select, used to steer data to and from the macrocell and the external data bus. (CORESYNC usually LOW for ARM7TDMI-S, HIGH for ARM7TDMI validationCOREFLOW usually HIGH for ARM7TDMI-S, LOW for ARM7TDMI)Input
BusSEQCPSEQIndicates sequential access to memory. 
BusWAIT2CFGMEM3WAIT (ARM7TDMI-S memory configuration)Input
BusWAITSELCFGMEM2Wait source select, if HIGH, selects WAIT2 instead of nWAIT (ARM7TDMI-S CFGMEM[3:0] is usually b01)Input
Bus CPnTRANS-Memory translation (active LOW to indicate that the processor is in User mode) (ARM7TDMI only)Output
ClockECLKEN-Clock output enable (ARM7TDMI only)Output
ClockECLKCLKENCOREClock output. In normal mode, this is MCLK output from the core. In debug mode ECLK is generated internally from TCK.Output
ClockMCLKCLKLOClock to test chip. Times all memory accesses and internal operations. Input
DebugBREAKPT-Pulling this signal HIGH causes a conditional request for the processor to enter debug state (ARM7TDMI only)Input
DebugCOMMRXRAMA4ICE communications receive buffer not empty (ARM7TDMI-S RAM[4] is a memory address)Output
DebugCOMMTXRAMA3ICE communications transmit buffer empty (ARM7TDMI-S RAM[3] is a memory address)Output
DebugDBGACKDBGACKDebug acknowledgeOutput
DebugDBGENDBGENDebug enableInput
Debug-DBGEXT[1:0]ICE external inputs (ARM7TDMI-S only)Input
DebugDBGINSTRVALIDDBGINSTRVALIDInstruction executed. Goes HIGH for one cycle for each instruction committed to the execute stage of the pipelineOutput
DebugDBGnEXEC Current instruction is not being executedOutput
DebugDBGRQDBGRQDebug requestInput
DebugDBGRQI-Internal debug request, this signal is the logical OR of DBGRQ and bit 1 of the debug control register (ARM7TDMI only)Output
DebugDBGRNG[1:0]DBGRNG[1:0]ICE range outOutput
DebugDBGTCKEN-Test clock enable (ARM7TDMI only)Input
DebugEXTERN[1:0]DBGEXT0, DBGEXT1Embedded ICD EXTERN debug qualifiers (tie LOW if not required)Input
DebugHIGHZOE_NTri-state test chip signals. If the HIGHZ instruction has been loaded into the TAP controller, this signal is HIGH.Input
DebugIR[3:0]WBYTE[3:0]_NInstruction register, reflects the current instruction loaded into the TAP controller instruction register. (ARM7TDMI-S is memory write control)Output
DebugISYNCCFGBOOTSynchronous interrupts, set HIGH if nIRQ and nFIQ are synchronous to the processor clock. (ARM7TDMI-S is configuration control)Input
DebugnENOUTIXIO_NNot enable output for coprocessor transfer, driven LOW during a coprocessor register transfer C cycle from the Embedded ICE communications channel processorOutput
DebugnEXECDBGnEXECNot executed. Indicates that the instruction in the execution unit is not being executedOutput
DebugnTDOENnTDOENEnable TDO tristate bufferOutput
DebugRANGEOUT[1:0]RAMA[10:9]EmbeddedICE rangeout qualifier outputs for ARM7TDMI. (Equivalent ARM7S signals are DBGRNG[1:0]) (ARM7TDMI-S RAMA[10:9] are RAM addresses)Output
DebugSCANENABLESCANENABLEScan test path enable for test pattern generationInput
DebugSCREG[3:0]RAMA[8:5]Scan chain register, reflects the ID number of the scan chain selected by the TAP controller (ARM7TDMI-S RAMA[8:5] are RAM addresses)Output
DebugTAPSM[3:0]-TAP controller state machine, reflects the current state of the TAP controller. (ARM7TDMI only)Output
DebugTBEINPUT116Test bus enable, if LOW, D[31:0], A[31:0], LOCK, MAS[1:0], nRW, nTRANS, and nOPC are set to high impedance.Input
DebugTCK[2:1]ROMB[1:0]TCK phase 1 and 2Output
DebugTEST[3:0]RAMDISABLE, RAS1_N, EXP_N, SCANOUTTest signals related to internal bus MD[0], MDOUT[31], and chip delays. (ARM7TDMI-S signals are memory control, if RAMDISABLE is HIGH, the memory controller in the ARM7TDMI-S test chip is disables and the pin function reverts to the ARM7TDMI definition.)-
InterruptnFIQnFIQExternal fast interrupt (active LOW)Input
InterruptnIRQnIRQExternal interrupt (active LOW)Input
JTAGARM_nTRSTDBGnTRSTTest reset to core, TAP and ICEInput
JTAGARM_TDIDGBTDIBoundary scan InputInput
JTAGARM_DBGRQIRTCKDebug request (ARM7TDMI-S return JTAG clock)Input
JTAGARM_TDODBGTDOBoundary scan OutputOutput
JTAGARM_TMSDBGTMSICE mode selectInput
JTAGDBBREAK ICE breakpoint/watchpoint indicatorInput
MemoryNC[2:0]RAMA0, RAMA1, RAMA2Reserved signals for ARM7TDMI (ARM7TDMI-S RAM[2:1] are memory addresses)Output
MiscBIGENDCFGBIGENDSelects big endian memory mode if HIGHInput
PowerARM_VDDCOREVDDCOREVoltage level used for processor coreInput
PowerARM_VDDIOVDDIOVoltage level used for input and output signalsInput
ResetnRESETnRESETReset input - asynchronousInput

Figure 7.2 shows the internal clock signals.

Figure 7.2. Test chip internal clock signals

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