7.6.4. Disabling the test chip output signals

The test chip on the CT7TDMI Core Tile can be disabled by driving the BCE signal HIGH. This tri-states all output signals from the Core Tile. Any header signals that are connected directly to the test chip can be used for other purposes by tiles connected above and below the Core Tile.

If the test chip is disabled, the PLD on the Core Tile can still be used to control header signals through the fold and thru switches and to provide access to the memory expansion connectors.


The BCE signal is not available on the test chip used on the CT7TDMI-S Core Tile.

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