7.7.1. Core Tile PLD signals

The PLD on the Core Tile performs the following functions:

The PLD is controlled by the serial interface signals listed in Table 7.6. These signals typically connect to an attached Logic Tile or IM-LT3 Interface Module. The FPGA in the external tile contains registers that hold the values to send to the PLD and received values from the PLD. The FPGA also provides the serialization and deserialization logic required by interface

Table 7.6. PLD control signals

SignalDescription
PLDCLKClocks data into or out of the PLD
PLDD1Serial data input to PLD
PLDD0Serial data output from PLD
PLDRESETnReset selects mode for PLD (LOW is startup, HIGH is runtime configuration)

The Core Tile PLD manages the Core Tile configuration and status signals listed in Table 7.7

Table 7.7. PLD configuration signals

SignalDirectionFunction
ZCTL[3:0]PLD outputZ Through control (see Through/Break control for HDRZ)
CLKSEL[4:0]PLD outputClock selection (see Clocks)
DACnCS[1:0]PLD outputChip select to DAC
DAC_DIN[1:0]PLD outputData to DAC (see Setting the VDDCORE voltage)
ADC_nCSPLD outputChip select to ADC
ADC_CLKPLD inputClock for data from ADC
ADC_SSTRBPLD inputStrobe for ADC. Indicates that a conversion has finished
ADC_DOUTPLD inputData from ADC (see Reading the voltages and currents)
ADC_DINPLD outputData to ADC (see Reading the voltages and currents)
nX_FOLD[1:0], nX_THRU[1:0]PLD outputSignal passthrough and fold switches for HDRX (see Through/break control for HDRX)
nY_FOLD[1:0], nY_THRU[1:0]PLD outputSignal passthrough and fold switches for HDRY (see Through/Break control for HDRY)
nZ_FOLD, nZ_THRUPLD outputSignal passthrough and fold switches for HDRZ (see Through/Break control for HDRZ)
MAN_ID[3:0]PLD inputBoard identification from resistor links. This is set at manufacture and identifies the board build.
PWR_nSHDN[2:0]PLD outputShutdown to the Vdd core power supplies (see Power supply control)
BCE, ABE, EEBE, EDBE, EABE, TBE,PLD outputDisable test chip by tri-stating all output pins (see Disabling the test chip output signals)

PLD function at power on

At power-on-reset, a controller in an external tile sends a configuration sequence to the PLD on the Core Tile as shown in Figure 7.11. The PLD control signals are described in Table 7.6.

Figure 7.11. Power on signals to the Core Tile PLD

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Table 7.8 lists the configuration and status signals that are received by or transmitted from the PLD at power on (after nSYSPOR goes HIGH).

Table 7.8. Power-on configuration signals by clock cycle

ClockPLDD1PLDD0Description
-LOWLOWNo activity while nSYSPOR is LOW
0LOWLOWFirst rising edge of clock after nSYSPOR goes HIGH
1ZCTL[3]MANID[3]ZCTL data is clocked into the PLD and the state of the MANID links is clocked out of the PLD.
2ZCTL[2]MANID[2]
3ZCTL[1]MANID[1]
4ZCTL[0]MANID[0]
5TCENABLEPLDID[3]

TCENABLE collectively controls the test chip bus output enables:

ABE

Address bus enable

BCE

BC external output enable

EEBE

External enable

EDBE

External data bus enable

EABE

Extrnal address bus enable

TBE

Test bus enable

6CLKSEL[4]PLDID[2]

CLKSEL multiplexer data is clocked into the PLD and the internal PLD ID is clocked out.

7CLKSEL[3]PLDID[1] 
8CLKSEL[2]PLDID[0] 
9CLKSEL[1]PGOOD 
10CLKSEL[0] 
11nX_THRU[1] 
12nX_THRU[0] 
13nX_FOLD[1] 
14nX_FOLD[0] 
15nY_THRU[1] 
16nY_THRU[0] 
17nY_FOLD[1] 
18nY_FOLD[0] 
19nZ_THRU 
20nZ_FOLD 
21 
22LOWLOWNo further activity until nSYSRST goes HIGH

PLD function after power on

After the power-on configuration finishes, the PLD is inactive until the nSYSRST signal goes HIGH. If nSYSRST is HIGH, The PLD continuously receives DAC packets from the serial interface and transmits ADC packets to the serial interface as shown in Figure 7.12.

Figure 7.12. ADC and DAC data stream

ADC and DAC data stream

Note

After nSYSRST goes HIGH, the ADC and DAC data packets repeat continuously.

nSYSRST is an external signal from an attached motherboard.

The format of the ADC packet is shown in Figure 7.13.

Figure 7.13. ADC packet format

ADC packet format

The format of the DAC packet is shown in Figure 7.14.

Figure 7.14. DAC packet format

DAC packet format

Table 7.9 lists the PLD input and output signals after nSYSPOR goes HIGH.

Table 7.9. Run configuration signals by clock cycle

ClockPLDD1 (PLD input)PLDD0 (PLD output)Description
-LOWLOWNo activity while nSYSPOR is LOW
0-ADCSELA[2]

First cycle after nSYSPOR goes HIGH. The DACSEL signals select which DAC value is transmitted in the current packet.

The value of the ADCSEL signals indicate the ADC value that is transmitted in the current packet.

1DACSELA[1]ADCSELA[2]
2DACSELA[0]ADCSELA[1]
3LOWADCSELA[1]
4DACDIN[7]ADCSELA[0]Start of DAC data.
5DACDIN[6]ADCSELA[0] 
6DACDIN[5]LOW 
7DACDIN[4]LOW 
8DACDIN[3]LOW 
9DACDIN[2]LOW 
10DACDIN[1]LOW 
11DACDIN[0]LOWEnd of first input packet
12-LOW 
13LOWLOW 
14DACSELA[1]LOWSecond DAC packet starts with DAC selection bits.
15DACSELA[0]LOW 
16LOWHIGH 
17DACDIN[7]HIGHDAC data starts.
18DACDIN[6]LOW 
19DACDIN[5]LOW 
20DACDIN[4]ADC_DOUTA[11]ADC data starts.
21DACDIN[3]ADC_DOUTA[11] 
22DACDIN[2]ADC_DOUTA[10] 
23DACDIN[1]ADC_DOUTA[10] 
24DACDIN[0]ADC_DOUTA[9] 
25-ADC_DOUTA[9] 
26LOWADC_DOUTA[8] 
27DACSELA[1]ADC_DOUTA[8]DAC data ends.
28DACSELA[0]ADC_DOUTA[7] 
29LOWADC_DOUTA[7] 
30DACDIN[7]ADC_DOUTA[6]Third DAC packet starts.
31DACDIN[6]ADC_DOUTA[6] 
32DACDIN[5]ADC_DOUTA[5] 
33DACDIN[4]ADC_DOUTA[5] 
34DACDIN[3]ADC_DOUTA[4] 
35DACDIN[2]ADC_DOUTA[4] 
36DACDIN[1]ADC_DOUTA[3]Start of DAC data
37DACDIN[0]ADC_DOUTA[3] 
38-ADC_DOUTA[2] 
39LOWADC_DOUTA[2] 
40DACSELA[1]ADC_DOUTA[1] 
41DACSELA[0]ADC_DOUTA[1] 
42LOWADC_DOUTA[0] 
43DACDIN[7]ADC_DOUTA[0]Fourth DAC packet starts. End of ADC data.
44DACDIN[6]LOW 
45DACDIN[5]LOW 
46DACDIN[4]LOW 
47DACDIN[3]LOW 
48DACDIN[2]LOW 
49DACDIN[1]PGOODPower good (always HIGH)
50DACDIN[0]LOWEnd of ADC packet.

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