The PLD on the Core Tile performs the following functions:
loading data to the DACs that control the programmable power supplies (see Power supply control)
reading data from the ADCs that monitor the test chip voltages (see Reading the voltages and currents)
controlling the clock selection multiplexors (see Clocks)
isolating HDRZ signals (see Through/Break control for HDRZ)
tri-stating all of the test chip outputs (see Disabling the test chip output signals)
selecting the test chip interface to the DATA[31:0] signals (see Isolation and foldover of header signals)
The PLD is controlled by the serial interface signals listed in Table 7.6. These signals typically connect to an attached Logic Tile or IM-LT3 Interface Module. The FPGA in the external tile contains registers that hold the values to send to the PLD and received values from the PLD. The FPGA also provides the serialization and deserialization logic required by interface
Table 7.6. PLD control signals
| Signal | Description |
|---|---|
| PLDCLK | Clocks data into or out of the PLD |
| PLDD1 | Serial data input to PLD |
| PLDD0 | Serial data output from PLD |
| PLDRESETn | Reset selects mode for PLD (LOW is startup, HIGH is runtime configuration) |
The Core Tile PLD manages the Core Tile configuration and status signals listed in Table 7.7
Table 7.7. PLD configuration signals
| Signal | Direction | Function |
|---|---|---|
| ZCTL[3:0] | PLD output | Z Through control (see Through/Break control for HDRZ) |
| CLKSEL[4:0] | PLD output | Clock selection (see Clocks) |
| DACnCS[1:0] | PLD output | Chip select to DAC |
| DAC_DIN[1:0] | PLD output | Data to DAC (see Setting the VDDCORE voltage) |
| ADC_nCS | PLD output | Chip select to ADC |
| ADC_CLK | PLD input | Clock for data from ADC |
| ADC_SSTRB | PLD input | Strobe for ADC. Indicates that a conversion has finished |
| ADC_DOUT | PLD input | Data from ADC (see Reading the voltages and currents) |
| ADC_DIN | PLD output | Data to ADC (see Reading the voltages and currents) |
| nX_FOLD[1:0], nX_THRU[1:0] | PLD output | Signal passthrough and fold switches for HDRX (see Through/break control for HDRX) |
| nY_FOLD[1:0], nY_THRU[1:0] | PLD output | Signal passthrough and fold switches for HDRY (see Through/Break control for HDRY) |
| nZ_FOLD, nZ_THRU | PLD output | Signal passthrough and fold switches for HDRZ (see Through/Break control for HDRZ) |
| MAN_ID[3:0] | PLD input | Board identification from resistor links. This is set at manufacture and identifies the board build. |
| PWR_nSHDN[2:0] | PLD output | Shutdown to the Vdd core power supplies (see Power supply control) |
| BCE, ABE, EEBE, EDBE, EABE, TBE, | PLD output | Disable test chip by tri-stating all output pins (see Disabling the test chip output signals) |
At power-on-reset, a controller in an external tile sends a configuration sequence to the PLD on the Core Tile as shown in Figure 7.11. The PLD control signals are described in Table 7.6.
Table 7.8 lists the configuration and status signals that are received by or transmitted from the PLD at power on (after nSYSPOR goes HIGH).
Table 7.8. Power-on configuration signals by clock cycle
| Clock | PLDD1 | PLDD0 | Description |
|---|---|---|---|
| - | LOW | LOW | No activity while nSYSPOR is LOW |
| 0 | LOW | LOW | First rising edge of clock after nSYSPOR goes HIGH |
| 1 | ZCTL[3] | MANID[3] | ZCTL data is clocked into the PLD and the state of the MANID links is clocked out of the PLD. |
| 2 | ZCTL[2] | MANID[2] | |
| 3 | ZCTL[1] | MANID[1] | |
| 4 | ZCTL[0] | MANID[0] | |
| 5 | TCENABLE | PLDID[3] | TCENABLE collectively controls the test chip bus output enables:
|
| 6 | CLKSEL[4] | PLDID[2] | CLKSEL multiplexer data is clocked into the PLD and the internal PLD ID is clocked out. |
| 7 | CLKSEL[3] | PLDID[1] | |
| 8 | CLKSEL[2] | PLDID[0] | |
| 9 | CLKSEL[1] | PGOOD | |
| 10 | CLKSEL[0] | − | |
| 11 | nX_THRU[1] | − | |
| 12 | nX_THRU[0] | − | |
| 13 | nX_FOLD[1] | − | |
| 14 | nX_FOLD[0] | − | |
| 15 | nY_THRU[1] | − | |
| 16 | nY_THRU[0] | − | |
| 17 | nY_FOLD[1] | − | |
| 18 | nY_FOLD[0] | − | |
| 19 | nZ_THRU | − | |
| 20 | nZ_FOLD | − | |
| 21 | − | − | |
| 22 | LOW | LOW | No further activity until nSYSRST goes HIGH |
After the power-on configuration finishes, the PLD is inactive until the nSYSRST signal goes HIGH. If nSYSRST is HIGH, The PLD continuously receives DAC packets from the serial interface and transmits ADC packets to the serial interface as shown in Figure 7.12.
Note
After nSYSRST goes HIGH, the ADC and DAC data packets repeat continuously.
nSYSRST is an external signal from an attached motherboard.
The format of the ADC packet is shown in Figure 7.13.
The format of the DAC packet is shown in Figure 7.14.
Table 7.9 lists the PLD input and output signals after nSYSPOR goes HIGH.
Table 7.9. Run configuration signals by clock cycle
| Clock | PLDD1 (PLD input) | PLDD0 (PLD output) | Description |
|---|---|---|---|
| - | LOW | LOW | No activity while nSYSPOR is LOW |
| 0 | - | ADCSELA[2] | First cycle after nSYSPOR goes HIGH. The DACSEL signals select which DAC value is transmitted in the current packet. The value of the ADCSEL signals indicate the ADC value that is transmitted in the current packet. |
| 1 | DACSELA[1] | ADCSELA[2] | |
| 2 | DACSELA[0] | ADCSELA[1] | |
| 3 | LOW | ADCSELA[1] | |
| 4 | DACDIN[7] | ADCSELA[0] | Start of DAC data. |
| 5 | DACDIN[6] | ADCSELA[0] | |
| 6 | DACDIN[5] | LOW | |
| 7 | DACDIN[4] | LOW | |
| 8 | DACDIN[3] | LOW | |
| 9 | DACDIN[2] | LOW | |
| 10 | DACDIN[1] | LOW | |
| 11 | DACDIN[0] | LOW | End of first input packet |
| 12 | - | LOW | |
| 13 | LOW | LOW | |
| 14 | DACSELA[1] | LOW | Second DAC packet starts with DAC selection bits. |
| 15 | DACSELA[0] | LOW | |
| 16 | LOW | HIGH | |
| 17 | DACDIN[7] | HIGH | DAC data starts. |
| 18 | DACDIN[6] | LOW | |
| 19 | DACDIN[5] | LOW | |
| 20 | DACDIN[4] | ADC_DOUTA[11] | ADC data starts. |
| 21 | DACDIN[3] | ADC_DOUTA[11] | |
| 22 | DACDIN[2] | ADC_DOUTA[10] | |
| 23 | DACDIN[1] | ADC_DOUTA[10] | |
| 24 | DACDIN[0] | ADC_DOUTA[9] | |
| 25 | - | ADC_DOUTA[9] | |
| 26 | LOW | ADC_DOUTA[8] | |
| 27 | DACSELA[1] | ADC_DOUTA[8] | DAC data ends. |
| 28 | DACSELA[0] | ADC_DOUTA[7] | |
| 29 | LOW | ADC_DOUTA[7] | |
| 30 | DACDIN[7] | ADC_DOUTA[6] | Third DAC packet starts. |
| 31 | DACDIN[6] | ADC_DOUTA[6] | |
| 32 | DACDIN[5] | ADC_DOUTA[5] | |
| 33 | DACDIN[4] | ADC_DOUTA[5] | |
| 34 | DACDIN[3] | ADC_DOUTA[4] | |
| 35 | DACDIN[2] | ADC_DOUTA[4] | |
| 36 | DACDIN[1] | ADC_DOUTA[3] | Start of DAC data |
| 37 | DACDIN[0] | ADC_DOUTA[3] | |
| 38 | - | ADC_DOUTA[2] | |
| 39 | LOW | ADC_DOUTA[2] | |
| 40 | DACSELA[1] | ADC_DOUTA[1] | |
| 41 | DACSELA[0] | ADC_DOUTA[1] | |
| 42 | LOW | ADC_DOUTA[0] | |
| 43 | DACDIN[7] | ADC_DOUTA[0] | Fourth DAC packet starts. End of ADC data. |
| 44 | DACDIN[6] | LOW | |
| 45 | DACDIN[5] | LOW | |
| 46 | DACDIN[4] | LOW | |
| 47 | DACDIN[3] | LOW | |
| 48 | DACDIN[2] | LOW | |
| 49 | DACDIN[1] | PGOOD | Power good (always HIGH) |
| 50 | DACDIN[0] | LOW | End of ADC packet. |
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