7.7. Overview of Core Tile configuration

The clock sources, and voltages levels on the Core Tile are configurable from input signals on the header connectors and signals output from the on-board PLD. In a production ASIC, core configuration is typically static and the core configuration signals are tied HIGH or LOW and the voltage and clocks are fixed. However, the Core Tile allows you to program these signals for experimentation.

There are several ways that Core Tile configuration occurs:

To change the configuration of the processor, program the appropriate values in the control registers implemented in the FPGA on the Logic Tile (or IM-LT3). Depending on the test chip present in the Core Tile, the contents of registers in the test chip might require modification. (See the application note for your product configuration for details on the control registers.)

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