3.4.2. Overview of clock signals

The clock related signals are summarized in Table 3.5.

Table 3.5. Clock-related signals on Core Tile

SignalDirectionDescription
CLK-Internal test chip clock from the PLL bypass multiplexer
CLK_GLOBALInput/output/thruA global clock shared with all tiles in the stack. Each tile can accept or drive the signal. HCLKEXT4 can drive this signal.
CLK_NEG_DNInput/output/thruA clock signal routed from the upper header (CLK_NEG_DN_IN) to the lower header (CLK_NEG_DN_OUT). The Core Tile can replace CLK_NEG_DN_OUT with HCLKEXT1.
CLK_NEG_UPInput/output/thruA clock signal routed from the lower header (CLK_NEG_UP_IN) to the upper header (CLK_NEG_UP_OUT). The Core Tile can replace CLK_NEG_UP_OUT with HCLKEXT0.
CLK_POS_UP, CLK_POS_DN, CLK_UP_THRU, CLK_OUT_PLUS1, CLK_OUT_PLUS2, CLK_IN_PLUS1, CLK_IN_PLUS1, and CLK_DN_THRU ThroughThese Logic Tile clock signals are not used by the Core Tile. They are passed through the Core Tile unmodified for use by other tiles.
CLKSEL[5:0]Local outputs from PLDThese signals (from the PLD) control the clock-selection multiplexors.
HCLK-

Internal test chip local memory clock output (not present on all test chips).

HCLKDIV[2:0]Input/throughRatio of AHB clock to CLK.
HCLKEXT[4:0]OutputSome test chips output buffered versions of HCLK as HCLKEXT[4:0].
HCLKINInput/throughFor some test chips, the internal AHB clock is supplied directly from this pin and is not divided down from the internal CLK signal.
PLDCLKInputClocks configuration data into (and status data out of) the PLD on the Core Tile.
PLLCTRL[1:0]Input/throughPLL control (typically power down and enable signals)
PLLFBDIV[7:0]Input/throughPLL feedback divisor
PLLLOCK In-lock indication from PLL
PLLOUTDIV[3:0]Input/throughPLL output divider. The output of this divider is the internal CLK signal.
REFCLK-A reference clock to the test chip clock-dividers, driven from either the XREFCLK_DN or XREFCLK_UP inputs
X_CLK_UP, X_CLK_DNOutputThe test chip HCLKEXT2 to the upper header as X_CLK_UP and HCLKEXT3 to the lower header as X_CLK_DN.
X_HCLKIN_UP, X_HCLKIN_DNInputX_HCLKIN_UP from the lower header or X_HCLKIN_DN from the upper header can be selected as the source of HCLKIN to the test chip.
X_REFCLK_UP, X_REFCLK_DNInputX_REFCLK_UP from the lower header or X_REFCLK_DN from the upper header can be selected as the source of REFCLK to the test chip.

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