5.3.4. Block disables

Table 5.4 lists block disables controlled from the Configuration Register and defined for the memory block. The programming of these registers is described in Configuration Register.

Table 5.4. External control inputs

SignalDescription
BLKDISABL[5]Disables the AHBRAM0 and AHBRAM1 primary test chip RAM blocks. Accesses are presented on the test chip AHB interface if this bit is configured HIGH.
BLKDISABL[4]Disables the AHBETB Mem address range. Accesses are presented on the test chip AHB interface if this bit is configured HIGH.
BLKDISABL[3]Disables the AHBETB Reg address range. The accesses are presented on the test chip AHB interface if this bit is configured HIGH.
BLKDISABL[2]Disables the AHBPCAPT block. Accesses are presented on the test chip AHB interface if this bit is configured HIGH.
BLKDISABL[1]Disables the AHBVIC block. Accesses are presented on the test chip AHB interface if this bit is configured HIGH.
BLKDISABL[0]Disables the AHBRAM2 secondary test chip RAM block. Accesses are presented on the test chip AHB interface if this bit is configured HIGH.

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