5.3.7. AHBPCAPT slave registers

Table 5.6 lists the addresses of the ARM1136JF-S AHBPCAPT Slave Registers.

Table 5.6. ARM1136JF-S AHBPCAPT Slave Registers

0x3F200000Read/writeARM1136JF-S Pin Capture Register
0x3F200010Read-onlyTest Chip Memory Size Register
0x3F200020Read-onlyInstruction AHB Port Register 0
0x3F200024Read-onlyInstruction AHB Port Register 1
0x3F200028Read-onlyInstruction AHB Port Register 2
0x3F200030Read-onlyData Read AHB Port Register 0
0x3F200034Read-onlyData Read AHB Port Register 1
0x3F200038Read-onlyData Read AHB Port Register 2
0x3F200040Read-onlyData Write AHB Port Register 0
0x3F200044Read-onlyData Write AHB Port Register 1
0x3F200048Read-onlyData Write AHB Port Register 2
0x3F200050Read-onlyDMA AHB Port Register 0
0x3F200054Read-onlyDMA AHB Port Register 1
0x3F200058Read-onlyDMA AHB Port Register 2
0x3F200060Read-onlyPeripheral AHB Port0 Register
0x3F200064Read-onlyPeripheral AHB Port1 Register
0x3F200068Read-onlyPeripheral AHB Port2 Register
0x3F200080Read/writeClock Generator Control Register
0x3F2000C0Read/writeTest Chip Control Register
0x3F200100Read-onlyETM11RV Pin Capture1 Register
0x3F200104Read-onlyETM11RV Pin Capture2 Register
0x3F200108Read-onlyETM11RV Pin Capture3 Register
0x3F200110Read/writeETM11RV Pin Control1 Register
0x3F200114Read/writeETM11RV Pin Control2 Register
0x3F200118Read/writeETM11RV Pin Control3 Register
0x3F20011CRead/writeETM11RV Pin Control4 Register

Table 5.7 lists the Pin Capture Register bit allocation.

Table 5.7. Pin Capture Register bit allocation

BitPinsReset Value
[31:24]Reserved, should be zeroUnpredictable
[7:5]Reserved, should be zeroUnpredictable
[0]Sticky STANDBYWFIUnpredictable

The Sticky STANDBYWFI bit is set if STANDBYWFI has been asserted in any cycle since the value was written by the core.

Table 5.8 lists the Test Chip Memory Size Register bit allocation.

Table 5.8. Test Chip Memory Size Register

[4:0]Test chip RAM size

Table 5.9 lists the valid test chip RAM size values.

Table 5.9. Valid test chip RAM sizes


The AHB port registers read the values of the HBSTRB[7:0], HUNALIGN, and HSIDEBAND signals to the last three non-sequential AHB transfers that have occurred for each port. The values are held as follows:

The registers therefore act as FIFOs. Table 5.10 lists the contents of each AHB Port Register.

Table 5.10. Contents of each AHB Port Register

[13]WRITEBACK (Data Write Port only. Other ports are UNP)
[7:0]HBSTRB[7:0] for the Peripheral Port bits [7:4] are UNP

Table 5.11 lists the Test Chip Control Register bit allocations.

Table 5.11. Test Chip Control Register

BitFunctionReset value
[31:1]Reserved, should be zeroUnpredictable
[0]VIC enable0

The VIC is disabled by default. This means that no programming of the VIC is required to connect nFIQX and nIRQX directly to the ARM1136JF-S core.

Table 5.12 lists the ETM11RV Pin Capture1 Register bit allocation.

Table 5.12. ETM11RV Pin Capture1 Register

Bit FunctionReset value
[31:10]Reserved, should be zeroUnpredictable

Table 5.13 lists the ETM11RV Pin Capture2 Register bit allocation.

Table 5.13. ETM11RV Pin Capture2 Register

Bit FunctionReset value
[31:2]Reserved, should be zeroUnpredictable

Table 5.14 lists the ETM11RV Pin Capture3 Register bit allocation.

Table 5.14. ETM11RV Pin Capture3 Register

Bit FunctionReset value
[31:8]Reserved, should be zeroUnpredictable

Table 5.15 lists the ETM11RV Pin Control1 Register bit allocation.

Table 5.15. ETM11RV Pin Control1 Register

Bit FunctionReset value
[31:4]Reserved, should be zeroUnpredictable

Table 5.16 lists the ETM11RV Pin Control2 Register bit allocation.

Table 5.16. ETM11RV Pin Control2 Register

BitFunctionReset value
[31:11]Reserved, should be zeroUnpredictable

Table 5.17 lists the ETM11RV Pin Control3 Register bit allocation.

Table 5.17. ETM11RV Pin Control3 Register

Bit FunctionReset value
[31:20]Reserved, should be zeroUnpredictable

Table 5.18 lists the ETM11RV Pin Control4 Register bit allocation.

Table 5.18. ETM11RV Pin Control4 Register

Bit FunctionReset value
[31:6]Reserved, should be zeroUnpredictable

Table 5.19 lists the EtmInputSel[1:0] encoding used to determine the source of ETMEXTINX.

Table 5.19. EtmInputSel[1:0] encoding

EtmInputSel[1:0]ETMEXTINX to ETM
b10(DBGACKX, PseudoRandom[2:0])
b11((b000, ETMEXTINX (test chip))

Table 5.20 lists the EtmInputSel[3:2] encoding used to determine the source of ETMEVNTBUS

Table 5.20. EtmInputSel[3:2] encoding

EtmInputSel[3:2]ETMEVNTBUS to ETM

Table 5.21 lists the EtmInputSel[5:4] encoding used to determine the source of ETMTRACEREADY

Table 5.21. EtmInputSel[5:4]

EtmInputSel[5:4]ETMEVNTBUS to ETM
b111 whenever an instruction is executed.

Configuration Register

The AHBPCAPT block contains the configuration register space. This space is programmed when the test chip is held in its lowest level of reset (that is, when ARM_nPORESET is asserted). The Configuration Register is a 32-bit register that is programmed to the value on HRDATAX signals at the rising edge of CONFIGINIT.

The Configuration Register is reset by asserting nCONFIGRST, and only when ARM_nPORESETX is asserted. The Configuration Register contents cannot be modified from software. Use the Clock Generator Control Register to change the clock frequency after power on.

Table 5.22 lists the bit allocation of the Configuration Register.

Table 5.22. Configuration Register

BitFunctionReset value (nCONFIGRST)
[31]Reserved, should be zero0
[30:8]Reset value of bits [28:8] of the Clock Generator Control Register0
[7:2]Test chip memory block disables0
[1:0]Reserved, should be zero0

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