Core Tile User Guide: 5.3.7. AHBPCAPT slave registers

5.3.7. AHBPCAPT slave registers

Table 5.6 lists the addresses of the ARM1136JF-S AHBPCAPT Slave Registers.

Table 5.6. ARM1136JF-S AHBPCAPT Slave Registers

Address	Type	Register
`0x3F200000`	Read/write	ARM1136JF-S Pin Capture Register
`0x3F200010`	Read-only	Test Chip Memory Size Register
`0x3F200020`	Read-only	Instruction AHB Port Register 0
`0x3F200024`	Read-only	Instruction AHB Port Register 1
`0x3F200028`	Read-only	Instruction AHB Port Register 2
`0x3F200030`	Read-only	Data Read AHB Port Register 0
`0x3F200034`	Read-only	Data Read AHB Port Register 1
`0x3F200038`	Read-only	Data Read AHB Port Register 2
`0x3F200040`	Read-only	Data Write AHB Port Register 0
`0x3F200044`	Read-only	Data Write AHB Port Register 1
`0x3F200048`	Read-only	Data Write AHB Port Register 2
`0x3F200050`	Read-only	DMA AHB Port Register 0
`0x3F200054`	Read-only	DMA AHB Port Register 1
`0x3F200058`	Read-only	DMA AHB Port Register 2
`0x3F200060`	Read-only	Peripheral AHB Port0 Register
`0x3F200064`	Read-only	Peripheral AHB Port1 Register
`0x3F200068`	Read-only	Peripheral AHB Port2 Register
`0x3F200080`	Read/write	Clock Generator Control Register
`0x3F2000C0`	Read/write	Test Chip Control Register
`0x3F200100`	Read-only	ETM11RV Pin Capture1 Register
`0x3F200104`	Read-only	ETM11RV Pin Capture2 Register
`0x3F200108`	Read-only	ETM11RV Pin Capture3 Register
`0x3F200110`	Read/write	ETM11RV Pin Control1 Register
`0x3F200114`	Read/write	ETM11RV Pin Control2 Register
`0x3F200118`	Read/write	ETM11RV Pin Control3 Register
`0x3F20011C`	Read/write	ETM11RV Pin Control4 Register

Table 5.7 lists the Pin Capture Register bit allocation.

Table 5.7. Pin Capture Register bit allocation

Bit	Pins	Reset Value
[31:24]	Reserved, should be zero	Unpredictable
[23:16]	DMAASID	`0`
[15:8]	COREASID	`0`
[7:5]	Reserved, should be zero	Unpredictable
[4]	DBGNOPWRDWN	`0`
[3]	CFGBIGENDPD	`0`
[2]	CFGBIGENDIRW	`0`
[1]	STANDBYWFI	`0`
[0]	Sticky STANDBYWFI	Unpredictable

The Sticky STANDBYWFI bit is set if STANDBYWFI has been asserted in any cycle since the value was written by the core.

Table 5.8 lists the Test Chip Memory Size Register bit allocation.

Table 5.8. Test Chip Memory Size Register

Bit	Function
[31:5]	Unpredictable
[4:0]	Test chip RAM size

Table 5.9 lists the valid test chip RAM size values.

Table 5.9. Valid test chip RAM sizes

Hex	Size
`0x07`	64KB
`0x08`	128KB
`0x09`	256KB
`0x0A`	512KB
`0x0B`	1MB
`0x0C`	2MB
`0x0D`	4MB
`0x0E`	8MB

The AHB port registers read the values of the HBSTRB[7:0], HUNALIGN, and HSIDEBAND signals to the last three non-sequential AHB transfers that have occurred for each port. The values are held as follows:

The most recent transfer is held in Register 0
The second most recent is held in Register 1
The third most recent is held in Register 2.

The registers therefore act as FIFOs. Table 5.10 lists the contents of each AHB Port Register.

Table 5.10. Contents of each AHB Port Register

BIT	Function
[31:14]	Unpredictable
[13]	WRITEBACK (Data Write Port only. Other ports are UNP)
[12:9]	HSIDEBAND[3:0]
[8]	HUNALIGN
[7:0]	HBSTRB[7:0] for the Peripheral Port bits [7:4] are UNP

Table 5.11 lists the Test Chip Control Register bit allocations.

Table 5.11. Test Chip Control Register

Bit	Function	Reset value
[31:1]	Reserved, should be zero	Unpredictable
[0]	VIC enable	`0`

The VIC is disabled by default. This means that no programming of the VIC is required to connect nFIQX and nIRQX directly to the ARM1136JF-S core.

Table 5.12 lists the ETM11RV Pin Capture1 Register bit allocation.

Table 5.12. ETM11RV Pin Capture1 Register

Bit	Function	Reset value
[31:10]	Reserved, should be zero	Unpredictable
[9]	nETMWFIREADY	`0`
[8:6]	ETMPORTMODE	`0`
[5:2]	ETMPORTSIZE	`0`
[1]	ETMEN	`0`
[0]	ETMPWRUP	`0`

Table 5.13 lists the ETM11RV Pin Capture2 Register bit allocation.

Table 5.13. ETM11RV Pin Capture2 Register

Bit	Function	Reset value
[31:2]	Reserved, should be zero	Unpredictable
[1:0]	ETMEXTOUTX	Unpredictable

Table 5.14 lists the ETM11RV Pin Capture3 Register bit allocation.

Table 5.14. ETM11RV Pin Capture3 Register

Bit	Function	Reset value
[31:8]	Reserved, should be zero	Unpredictable
[7:0]	ETMASICCTL	Unpredictable

Table 5.15 lists the ETM11RV Pin Control1 Register bit allocation.

Table 5.15. ETM11RV Pin Control1 Register

Bit	Function	Reset value
[31:4]	Reserved, should be zero	Unpredictable
[3:0]	EtmExtInRega	`0`

Table 5.16 lists the ETM11RV Pin Control2 Register bit allocation.

Table 5.16. ETM11RV Pin Control2 Register

Bit	Function	Reset value
[31:11]	Reserved, should be zero	Unpredictable
[10]	ORed into ETMWFIPENDING	`0`
[9:6]	ETMMAXPORTSIZE	`b0100`
[5:3]	ETMMAXEXTOUT	`b010`
[2:0]	ETMMAXEXTIN	`0`

Table 5.17 lists the ETM11RV Pin Control3 Register bit allocation.

Table 5.17. ETM11RV Pin Control3 Register

Bit	Function	Reset value
[31:20]	Reserved, should be zero	Unpredictable
[19:0]	EtmEvntBusRega	`0`

Table 5.18 lists the ETM11RV Pin Control4 Register bit allocation.

Table 5.18. ETM11RV Pin Control4 Register

Bit	Function	Reset value
[31:6]	Reserved, should be zero	Unpredictable
[5:0]	EtmInputSel	`0`

Table 5.19 lists the EtmInputSel[1:0] encoding used to determine the source of ETMEXTINX.

Table 5.19. EtmInputSel[1:0] encoding

EtmInputSel[1:0]	ETMEXTINX to ETM
`b00`	`0`
`b01`	EtmExtInReg
`b10`	(DBGACKX, PseudoRandom[2:0])
`b11`	((`b000`, ETMEXTINX (test chip))

Table 5.20 lists the EtmInputSel[3:2] encoding used to determine the source of ETMEVNTBUS

Table 5.20. EtmInputSel[3:2] encoding

EtmInputSel[3:2]	ETMEVNTBUS to ETM
`b00`	`0`
`b01`	EtmEvntBusReg
`b10`	PseudoRandom[19:0]
`b11`	ETMEVNTBUS from ARM1136JF-S

Table 5.21 lists the EtmInputSel[5:4] encoding used to determine the source of ETMTRACEREADY

Table 5.21. EtmInputSel[5:4]

EtmInputSel[5:4]	ETMEVNTBUS to ETM
`b00`	`1`
b01	PseudoRandom[0]
b10	`0`
b11	`1` whenever an instruction is executed.

Configuration Register

The AHBPCAPT block contains the configuration register space. This space is programmed when the test chip is held in its lowest level of reset (that is, when ARM_nPORESET is asserted). The Configuration Register is a 32-bit register that is programmed to the value on HRDATAX signals at the rising edge of CONFIGINIT.

The Configuration Register is reset by asserting nCONFIGRST, and only when ARM_nPORESETX is asserted. The Configuration Register contents cannot be modified from software. Use the Clock Generator Control Register to change the clock frequency after power on.

Table 5.22 lists the bit allocation of the Configuration Register.

Table 5.22. Configuration Register

Bit	Function	Reset value (nCONFIGRST)
[31]	Reserved, should be zero	`0`
[30:8]	Reset value of bits [28:8] of the Clock Generator Control Register	`0`
[7:2]	Test chip memory block disables	`0`
[1:0]	Reserved, should be zero	`0`

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