7.4.1. Clock multiplexors

Clock selection signals CLKSEL[5:0] and foldover control signals nX_FOLD1 and nX_THRU1 control the multiplexors on the Core Tile:

CLKSEL[0]

This selects between clocks on the upper or lower header connectors as the source for MCLK and the destination for ECLK.

CLKSEL[2:1]

This selects the source for MCLK. The input is either one of the clocks on the upper or lower header connector, ground, or the buffered CLK_GLOBAL.

CLKSEL[3]

If HIGH, the CLK_NEG_UP_OUT on the top header is connected to ground. If LOW, CLK_NEG_UP_OUT is driven by the CLK_NEG_UP_IN signal from the lower header on the Core Tile.

CLKSEL[4]

If HIGH, the CLK_NEG_DN_OUT on the lower header is connected to ground. If LOW, CLK_NEG_DN_OUT is driven by the CLK_NEG_DN_IN signal from the upper header on the Core Tile.

CLKSEL[5]

If HIGH, the X_ECLK_UP and X_MCLK_DN on the upper header are connected to the isolation switches for XL33 and XL32. If CLKSEL[5] is LOW and nX_THRU is HIGH, the signals on XL33 and XL32 can be used by the multiplexor as alternative source for MCLK and destination for ECLK.

nX_FOLD1

Connects signals on the upper header to signals on the lower header. If HIGH, X_ECLK_UP and X_MCLK_DN on the upper header are connected to the X147 and X146 (on both the upper and lower headers).

nX_THRU1

Enables signals onto the lower header. If CLKSEL[5] is LOW and nX_THRU is HIGH, the signals on XL33 and XL32 are connected to the multiplexors and can be used as an alternative source for MCLK and destination for ECLK.

See Core Tile PLD signals for details on controlling the CLKSEL[5:0] signals from the PLD using PLDCLK, PLDD0, and PLDD1. The MCLK and ECLK routing for values of CLKSEL[5:0] are listed in Table 7.4 and Table 7.5.

Table 7.4. MCLK clock source

CLKSEL[5:0] MCLK source
bxxx000CLK_NEG_UP_IN
bxxx001CLK_NEG_DN_IN
b0xx010X_MCLK_UP (This signal is connected to XL32 if nX_THRU1 is HIGH and is floating if nX_THRU1 is LOW)
b0xx011X_MCLK_DN (If nX_FOLD1 is HIGH X_MCLK_DN is also connected to X146.)
b1xx01xX_MCLK_DN and X_MCLK_DN are connected together. (If nX_THRU1 is HIGH, the signal can be sourced from either the upper or lower header. If nX_FOLD1 is HIGH X_MCLK_DN is also connected to X146.)
bxxx100GND (no clock input)
bxxx101GND (no clock input)
bxxx110CLK_GLOBAL
bxxx111CLK_GLOBAL

Table 7.5. ECLK destination

CLKSEL[5:0] ECLK output
b0xxxx0X_ECLK_UP (If nX_FOLD1 is HIGH X_ECLK_UP is connected to X147.)
b0xxxx1X_ECLK_DN (X_ECLK_DN is also connected to XL33 if nX_THRU1 is HIGH)
b1xxxxxBoth X_ECLK_UP and X_ECLK_DN. (X_ECLK_DN is also connected to XL33 if nX_THRU1 is HIGH. If nX_FOLD1 is HIGH X_ECLK_UP is also connected to X147.)

Figure 7.4. Test chip clock selection

Test chip clock selection

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