Core Tile User Guide

HBI-0131(CT926EJ-S and CT1136JF-S) HBI-0141 (CT7TDMI and CT7TDMI-S)


Table of Contents

Preface
About this document
Intended audience
Organization
Typographical conventions
Further reading
Feedback
Feedback on this document
Feedback on the ARM Core Tiles
1. Introduction
1. Introduction
1.1. About the Core Tiles
1.2. Overview of Core Tiles
1.2.1. System architecture
1.2.2. External logic
1.2.3. ARM processor test chip
1.2.4. PLD
1.2.5. Processor bus
1.2.6. Memory
1.2.7. Clock generation
1.2.8. JTAG and Trace
1.2.9. Power supply control
1.2.10. Links and indicators
1.3. Precautions
1.3.1. Ensuring safety
1.3.2. Preventing damage
2. Getting Started
2.1. Using the Core Tile with an Interface Module
2.2. Using the Core Tile with an Integrator Compact Platform baseboard
2.3. Using the Core Tile with a Versatile Baseboard
2.4. Using the Core Tile with a custom baseboard
2.5. Connecting power
2.5.1. Supplying power to an Interface Module
2.5.2. Supplying power to a baseboard
2.6. Connecting RealView ICE or Multi-ICE
2.6.1. Connecting a JTAG device to an Interface Module
2.6.2. Connecting a JTAG device to a baseboard
2.7. Connecting Trace
2. Printed Circuit Board HBI-0131 (CT926EJ-S and CT1136JF-S)
3. HBI-0131 Hardware Description
3.1. Core Tile architecture
3.2. ARM microprocessor test chip
3.3. Core Tile memory
3.3.1. Memory located inside test chip
3.3.2. Memory expansion boards
3.3.3. Memory map
3.4. Clocks
3.4.1. Clock multiplexors
3.4.2. Overview of clock signals
3.5. Power supply control
3.5.1. Resistor links for power supply
3.5.2. Setting the VDDCORE voltage
3.5.3. Reading the voltages and currents
3.6. Control of AHB data bus and HDRZ signals
3.6.1. Data read/write control for AHB data
3.6.2. Through/Break control for HDRZ
3.7. Overview of Core Tile configuration
3.7.1. Core Tile PLD signals
3.7.2. Configuration signals on HDRX
3.7.3. Core configuration from ARM CP15 and on-chip registers
3.8. JTAG support
3.8.1. JTAG signals
3.8.2. Debug communications interrupts
3.9. Embedded Trace support
4. HBI-0131 Features specific to the CT926EJ-S
4.1. ARM926EJ-S test chip characteristics
4.2. Clocks
4.3. Memory map
4.4. Voltage control
5. HBI-0131 Features specific to the CT1136JF-S
5.1. ARM1136JF-S test chip characteristics
5.2. Clocks
5.2.1. Test chip clock control
5.2.2. Synchronous/asynchronous clock control
5.3. AHB memory map
5.3.1. AHB matrix and memories block
5.3.2. External AHB interface
5.3.3. AHB address map
5.3.4. Block disables
5.3.5. AHB submodules
5.3.6. AHB slaves and support blocks
5.3.7. AHBPCAPT slave registers
5.4. Vectored Interrupt Controller (VIC) block
5.5. Voltage control
6. HBI-0131 Signal Descriptions
6.1. Header connectors
6.1.1. HDRX signals
6.1.2. HDRY signals
6.1.3. HDRZ
6.2. Memory expansion connector pinout
6.2.1. Memory expansion connector J6
6.2.2. Memory expansion connector J7
6.3. Trace Port connectors
6.4. Links and test points
6.4.1. Links
6.4.2. Test points
6.5. AHB bus timing specification
6.5.1. Core Tile timing and the AMBA Specification
6.5.2. Timing parameter tables
3. Printed Circuit Board HBI-0141 (CT7TDMI and CT7TDMI-S)
7. HBI-0141 Hardware Description
7.1. Core Tile architecture
7.2. ARM microprocessor test chip
7.3. Core Tile memory
7.3.1. Memory expansion boards
7.3.2. Memory map
7.4. Clocks
7.4.1. Clock multiplexors
7.5. Power supply control
7.5.1. Resistor links for power supply
7.5.2. Setting the VDDCORE voltage
7.5.3. Reading the voltages and currents
7.6. Isolation and foldover of header signals
7.6.1. Through/break control for HDRX
7.6.2. Through/Break control for HDRZ
7.6.3. Through/Break control for HDRY
7.6.4. Disabling the test chip output signals
7.7. Overview of Core Tile configuration
7.7.1. Core Tile PLD signals
7.8. JTAG support
7.8.1. JTAG signals
7.8.2. Debug communications interrupts
8. HBI-0141 Signal Descriptions
8.1. Header connectors
8.1.1. HDRX signals
8.1.2. HDRY signals
8.1.3. HDRZ
8.2. Memory expansion connector pinout
8.3. Links and test points
8.3.1. Links
8.3.2. Test points
A. Static Memory Expansion Board
A.1. About memory expansion
A.1.1. Memory board configuration
A.2. Fitting a memory board
A.3. EEPROM contents
A.4. Connector pinout
A.5. Mechanical layout
B. Specifications
B.1. Electrical specification
B.1.1. Bus interface characteristics
B.1.2. Current requirements
B.2. Mechanical details
Glossary

List of Figures

1.1. Core Tile layout
1.2. Core Tile and Integrator/IM-LT3
1.3. Typical system block diagram
2.1. Core Tile and an Integrator/IM-LT3
2.2. Core Tile, Logic Tile, and Integrator/IM-LT1
2.3. Core Tile, Integrator/IM-LT3, and Integrator/CP
2.4. Core Tile and a Versatile baseboard
2.5. Power connector on interface Module
2.6. Power connectors on Versatile/PB926EJ-S
2.7. Powering the assembled Integrator/CP system
2.8. JTAG connector on the Interface Module
2.9. JTAG connection to a Versatile/PB926EJ-S
2.10. Trace connection with RealView Trace
2.11. Trace connection with Multi-Trace
3.1. Core Tile block diagram
3.2. Core Tile clock signals
3.3. Test chip clock selection (CT926EJ-S)
3.4. Voltage control and monitoring
3.5. Voltage interconnection links
3.6. Programmable regulators
3.7. Voltage divider and current sense circuit
3.8. Read/write control
3.9. Through/break control
3.10. Power on signals to the Core Tile PLD
3.11. ADC and DAC data stream
3.12. ADC packet format
3.13. DAC packet format
3.14. JTAG clock and data signals
3.15. JTAG data flow in debug mode
3.16. JTAG data flow in config mode
3.17. JTAG reset signals
4.1. Clock signals
5.1. Clock selection
5.2. AHB matrix and bus organization
6.1. HDRX, HDRY, and HDRZ (upper) pin numbering
6.2. Memory expansion connectors
6.3. Mictor connector
6.4. Location of links (bottom)
6.5. Location of links (top)
6.6. Test point location
7.1. Core Tile block diagram
7.2. Test chip internal clock signals
7.3. Core Tile clock signals
7.4. Test chip clock selection
7.5. Voltage control and monitoring
7.6. Voltage interconnection links
7.7. Programmable regulators
7.8. HDRX through/break control
7.9. HDRZ through/break control
7.10. HDRY through/break control
7.11. Power on signals to the Core Tile PLD
7.12. ADC and DAC data stream
7.13. ADC packet format
7.14. DAC packet format
7.15. JTAG clock and data signals
7.16. Simplified data and clocks for debug mode (ARM7TDMI-S)
7.17. Simplified data and clocks for debug mode (ARM7TDMI)
7.18. Simplified data and clocks for config mode (ARM7TDMI and ARM7TDMI-S)
7.19. JTAG reset signals
8.1. HDRX, HDRY, and HDRZ (upper) pin numbering
8.2. Location of links (top)
8.3. Location of links (bottom)
8.4. Test point location
A.1. Static memory board block diagram
A.2. Memory board installation
A.3. Chip select information block
A.4. Static memory board layout
B.1. Board outline (top view)

List of Tables

1.1. Product combinations with Core Tile
3.1. Test chip signals
3.2. Memory size configuration
3.3. CLKSEL[5:0] signals and HCLKIN source
3.4. CLKSEL[5:0] signals and REFCLK source
3.5. Clock-related signals on Core Tile
3.6. Data bus switch function
3.7. PLD control signals
3.8. PLD configuration signals
3.9. Power-on configuration signals by clock cycle
3.10. Run configuration signals by clock cycle
3.11. Configuration signals on header connectors
3.12. JTAG signal description
4.1. Supply voltage connections
5.1. Clock Generator Control Register
5.2. AHB interfaces
5.3. Test chip address map
5.4. External control inputs
5.5. AHB slaves
5.6. ARM1136JF-S AHBPCAPT Slave Registers
5.7. Pin Capture Register bit allocation
5.8. Test Chip Memory Size Register
5.9. Valid test chip RAM sizes
5.10. Contents of each AHB Port Register
5.11. Test Chip Control Register
5.12. ETM11RV Pin Capture1 Register
5.13. ETM11RV Pin Capture2 Register
5.14. ETM11RV Pin Capture3 Register
5.15. ETM11RV Pin Control1 Register
5.16. ETM11RV Pin Control2 Register
5.17. ETM11RV Pin Control3 Register
5.18. ETM11RV Pin Control4 Register
5.19. EtmInputSel[1:0] encoding
5.20. EtmInputSel[3:2] encoding
5.21. EtmInputSel[5:4]
5.22. Configuration Register
5.23. Test chip interrupt routing
5.24. Supply voltage connections
6.1. Samtec part numbers
6.2. Signal differences between CT926EJ-S and 1136JF-S
6.3. HDRX signals
6.4. HDRY signals
6.5. HDRZ signals
6.6. Z memory connector signals
6.7. Y memory connector signals
6.8. Trace connector A J9
6.9. Trace connector B J10
6.10. Link function
6.11. JTAG links
6.12. Clock signal resistor links
6.13. Voltage resistor links
6.14. DDR SDRAM resistor links
6.15. Test point function
6.16. Clock and reset parameters
6.17. AHB slave input parameters
6.18. AHB slave output parameters
6.19. Bus master input timing parameters
6.20. Bus master output timing parameters
7.1. Overview of Core Tile signals
7.2. Test chip signals
7.3. Clock-related signals on Core Tile
7.4. MCLK clock source
7.5. ECLK destination
7.6. PLD control signals
7.7. PLD configuration signals
7.8. Power-on configuration signals by clock cycle
7.9. Run configuration signals by clock cycle
7.10. JTAG signal description
8.1. HDRX signals
8.2. HDRY signals
8.3. HDRZ signals
8.4. Resistor links for JTAG logic
8.5. Resistor links for clock signals
8.6. Resistor links for voltage selection
8.7. Resistor links for DDR SDRAM
8.8. Test point function
A.1. Memory width encoding
A.2. Chip Select information block
A.3. Example contents of a static memory expansion EEPROM
A.4. Static memory connector signals
B.1. Core Tile electrical characteristics
B.2. Current requirements

Proprietary Notice

Words and logos marked with® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The Core Tile generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision AOctober 2004First release (ARM926EJ-S and ARM1136JF-S versions)
Revision BFebruary 2005Second release (includes ARM7TDMI and ARM7TDMI-S)
Revision CAugust 2006Third release updated to fix various documentation defects
Revision DMay 2007Fourth release updated to fix various documentation defects
Revision EOctober 2007Fifth release updated to fix a documentation defect
Revision FJanuary 2009Sixth release updated to fix a documentation defect
Revision GJune 2011Seventh release updated to fix a documentation defect
Copyright © 2004-2011 ARM Limited. All rights reserved.ARM DUI 0273G
Non-ConfidentialID060911