Core Tile User Guide
HBI-0131(CT926EJ-S and CT1136JF-S) HBI-0141 (CT7TDMI and CT7TDMI-S)
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Part 2. Printed Circuit Board HBI-0131 (CT926EJ-S and CT1136JF-S)
Table of Contents
3. HBI-0131 Hardware Description
3.1. Core Tile architecture
3.2. ARM microprocessor test chip
3.3. Core Tile memory
3.3.1. Memory located inside test chip
3.3.2. Memory expansion boards
3.3.3. Memory map
3.4. Clocks
3.4.1. Clock multiplexors
3.4.2. Overview of clock signals
3.5. Power supply control
3.5.1. Resistor links for power supply
3.5.2. Setting the VDDCORE voltage
3.5.3. Reading the voltages and currents
3.6. Control of AHB data bus and HDRZ signals
3.6.1. Data read/write control for AHB data
3.6.2. Through/Break control for HDRZ
3.7. Overview of Core Tile configuration
3.7.1. Core Tile PLD signals
3.7.2. Configuration signals on HDRX
3.7.3. Core configuration from ARM CP15 and on-chip registers
3.8. JTAG support
3.8.1. JTAG signals
3.8.2. Debug communications interrupts
3.9. Embedded Trace support
4. HBI-0131 Features specific to the CT926EJ-S
4.1. ARM926EJ-S test chip characteristics
4.2. Clocks
4.3. Memory map
4.4. Voltage control
5. HBI-0131 Features specific to the CT1136JF-S
5.1. ARM1136JF-S test chip characteristics
5.2. Clocks
5.2.1. Test chip clock control
5.2.2. Synchronous/asynchronous clock control
5.3. AHB memory map
5.3.1. AHB matrix and memories block
5.3.2. External AHB interface
5.3.3. AHB address map
5.3.4. Block disables
5.3.5. AHB submodules
5.3.6. AHB slaves and support blocks
5.3.7. AHBPCAPT slave registers
5.4. Vectored Interrupt Controller (VIC) block
5.5. Voltage control
6. HBI-0131 Signal Descriptions
6.1. Header connectors
6.1.1. HDRX signals
6.1.2. HDRY signals
6.1.3. HDRZ
6.2. Memory expansion connector pinout
6.2.1. Memory expansion connector J6
6.2.2. Memory expansion connector J7
6.3. Trace Port connectors
6.4. Links and test points
6.4.1. Links
6.4.2. Test points
6.5. AHB bus timing specification
6.5.1. Core Tile timing and the AMBA Specification
6.5.2. Timing parameter tables