Core Tile User Guide

HBI-0131(CT926EJ-S and CT1136JF-S) HBI-0141 (CT7TDMI and CT7TDMI-S)

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Part 3. Printed Circuit Board HBI-0141 (CT7TDMI and CT7TDMI-S)

Table of Contents

7. HBI-0141 Hardware Description

7.1. Core Tile architecture

7.2. ARM microprocessor test chip

7.3. Core Tile memory

7.3.1. Memory expansion boards
7.3.2. Memory map

7.4. Clocks

7.4.1. Clock multiplexors

7.5. Power supply control

7.5.1. Resistor links for power supply
7.5.2. Setting the VDDCORE voltage
7.5.3. Reading the voltages and currents

7.6. Isolation and foldover of header signals

7.6.1. Through/break control for HDRX
7.6.2. Through/Break control for HDRZ
7.6.3. Through/Break control for HDRY
7.6.4. Disabling the test chip output signals

7.7. Overview of Core Tile configuration

7.7.1. Core Tile PLD signals

7.8. JTAG support

7.8.1. JTAG signals
7.8.2. Debug communications interrupts

8. HBI-0141 Signal Descriptions

8.1. Header connectors

8.1.1. HDRX signals
8.1.2. HDRY signals
8.1.3. HDRZ

8.2. Memory expansion connector pinout

8.3. Links and test points

8.3.1. Links
8.3.2. Test points

Copyright © 2004-2011 ARM Limited. All rights reserved.	ARM DUI 0273G
Non-Confidential	ID060911
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