4.11. Pseudo-instructions
The ARM assembler supports a number of pseudo-instructions
that are translated into the appropriate combination of ARM, Thumb,
or Thumb-2 instructions at assembly time.
The pseudo-instructions are described in the following sections:
ADR pseudo-instruction
Load a program-relative or register-relative address (short
range, position independent)
ADRL pseudo-instruction
Load a program-relative or register-relative address into
a register (medium range, position independent)
LDR pseudo-instruction
Load a register with a 32-bit constant value or an address
(unlimited range, but not position independent). Available for all
ARM architectures.
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