RealView® Developer Kit Assembler Guide 4.1. Instruction summary

4.1. Instruction summary

Table 4.1 gives an overview of the instructions available in the ARM and Thumb instruction sets. Use it to locate individual instructions and pseudo-instructions described in the rest of this chapter.

The § column in Table 4.1 shows the ARM architecture in which each instruction first appeared.

Table 4.1. Location of instructions

Mnemonic	Brief description	Page	§
`ADC`, `ADD`	Add with Carry, Add	ADD, SUB, RSB, ADC, SBC, and RSC	All
`ADR` pseudo-instruction	Load program or register-relative address (short range)	ADR pseudo-instruction	All
`ADRL` pseudo-instruction	Load program or register-relative address (medium range)	ADRL pseudo-instruction	All
`AND`	Logical AND	AND, ORR, EOR, and BIC	All
`ASR`	Arithmetic Shift Right	ASR, LSL, LSR, ROR, and RRX	All
`B`	Branch	B, BL, BX, BLX, and BXJ	All
`BIC`	Bit Clear	AND, ORR, EOR, and BIC	All
`BKPT`	Breakpoint	BKPT	5
`BL`	Branch with Link	B, BL, BX, BLX, and BXJ	All
`CDP`, `CDP2`	Coprocessor Data Processing operation	CDP and CDP2	All, 5
`CLZ`	Count leading zeros	CLZ	5
`CMN`, `CMP`	Compare Negative, Compare	CMP and CMN	All
`EOR`	Exclusive OR	AND, ORR, EOR, and BIC	All
`LDC`, `LDC2`	Load Coprocessor	LDC and STC	All, 5
`LDM`	Load Multiple registers	LDM and STM	All
`LDR`	Load Register instructions	Memory access instructions	All
`LDR` pseudo-instruction	Load Register pseudo-instruction	LDR pseudo-instruction	All
`LSL`, `LSR`	Logical Shift Left, Logical Shift Right	ASR, LSL, LSR, ROR, and RRX	All
`MCR`, `MCR2`, `MCRR`, `MCRR2`	Move from Register(s) to Coprocessor	MCR, MCR2, MCRR, and MCRR2	All, 5, 5E, 6
`MLA`, `MLS`	Multiply Accumulate, Multiply and Subtract	MUL and MLA	All
`MOV`	Move	MOV and MVN	All
`MRC`, `MRC2`	Move from Coprocessor to Register	MRC, MRC2, MRRC and MRRC2	All, 5
`MRS`	Move from PSR to register	MRS	All
`MSR`	Move from register to PSR	MSR	All
`MUL`	Multiply	MUL and MLA	All
`MVN`	Move Not	MOV and MVN	All
`NOP`	No Operation	NOP	All
`ORN`	Logical OR NOT	AND, ORR, EOR, and BIC	T2
`ORR`	Logical OR	AND, ORR, EOR, and BIC	All
`PUSH`, `POP`	PUSH, POP registers	PUSH and POP	All T
`QADD`, `QDADD`, `QDSUB`, `QSUB`	Saturating Arithmetic	QADD, QSUB, QDADD, and QDSUB	5ExP
`ROR`	Rotate Right Register	ASR, LSL, LSR, ROR, and RRX	All
`RSB`, `RSC`, `SBC`	Reverse Sub, Reverse Sub with Carry, Sub with Carry	ADD, SUB, RSB, ADC, SBC, and RSC	All
`SMI`	Secure Monitor Interrupt	SMI	Z
`SMLAL`	Signed Multiply Accumulate (64 <= 64 + 32 x 32)	UMULL, UMLAL, SMULL, and SMLAL	M
`SMLALxy`	Signed Multiply Accumulate (64 <= 64 + 16 x 16)	SMLAL`xy`	5ExP
`SMULL`	Signed Multiply (64 <= 32 x 32)	UMULL, UMLAL, SMULL, and SMLAL	M
`SMULxy`	Signed Multiply (32 <= 16 x 16)	SMUL`xy` and SMLA`xy`	5ExP
`SMULWy`	Signed Multiply (32 <= 32 x 16)	SMULW`y` and SMLAW`y`	5ExP
`STC`	Store Coprocessor	LDC and STC	All
`STC2`	Store Coprocessor	LDC2 and STC2	5ExP
`STM`	Store Multiple registers	LDM and STM	All
`STR`	Store Register instructions	Memory access instructions	All
`SUB`	Subtract	ADD, SUB, RSB, ADC, SBC, and RSC	All
`SWI`	Software Interrupt	SWI	All
`SWP`, `SWPB`	Swap registers and memory (ARM only)	SWP and SWPB	All
`TEQ`, `TST`	Test Equivalence, Test	TST and TEQ	All
`UMLAL`, `UMULL`	Unsigned Multiply Accumulate, Multiply	UMULL, UMLAL, SMULL, and SMLAL	M
	(64 <= 32 x 32 + 64), (64 <= 32 x 32)

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