RealView ® DeveloperKit Assembler Guide

Version 2.2


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback
Feedback on RealView Developer Kit
Feedback on this book
1. Introduction
1.1. About the RealView Developer Kit assemblers
1.1.1. ARM Assembly Language
1.1.2. Using the examples
2. Writing ARM Assembly Language
2.1. Introduction
2.1.1. Code examples
2.2. Overview of the ARM architecture
2.2.1. Architecture versions
2.2.2. ARM, Thumb, and Thumb-2 instruction sets
2.2.3. ARM and Thumb state
2.2.4. Processor mode
2.2.5. Registers
2.2.6. Instruction setoverview
2.2.7. Instruction capabilities
2.3. Structure of assembly language modules
2.3.1. Layout of assembly language source files
2.3.2. An example ARM assembly language module
2.3.3. Calling subroutines
2.4. Conditional execution
2.4.1. The ALU status flags
2.4.2. Conditional execution in ARM state
2.4.3. Example
2.4.4. Using conditional execution in ARMstate
2.4.5. Example of the use of conditional execution
2.4.6. The Q flag
2.5. Loading constants into registers
2.5.1. Direct loading withMOV and MVN
2.5.2. Loading with LDR Rd, =const
2.6. Loading addresses into registers
2.6.1. Direct loading with ADR and ADRL
2.6.2. Loading addresses withLDR Rd, = label
2.7. Load and store multiple register instructions
2.7.1. Load and store multiple instructionsavailable in ARM and Thumb
2.7.2. Implementing stackswith LDM and STM
2.7.3. Block copy with LDMand STM
2.8. Using macros
2.8.1. Test-and-branch macro example
2.8.2. Unsigned integer division macro example
2.9. Adding symbol versions
2.10. Using frame directives
2.11. Assembly Language changes
3. Assembler Reference
3.1. Command syntax
3.1.1. Obtaining a list of available options
3.1.2. AAPCS
3.1.3. Floating-point model
3.1.4. CPU names
3.1.5. FPU names
3.1.6. Memory access attributes
3.1.7. Pre-executing a SETdirective
3.1.8. Splitting long LDMs and STMs
3.1.9. Listing output to a file
3.1.10. Controlling the output of diagnosticmessages
3.1.11. Controlling exceptiontable generation
3.2. Format of source lines
3.3. Predefined register and coprocessornames
3.3.1. Predeclared register names
3.3.2. Predeclared program status register names
3.3.3. Predeclared floating-point register names
3.3.4. Predeclared coprocessor names
3.4. Built-in variables and constants
3.4.1. Determining the armasm version atassembly time
3.5. Symbols
3.5.1. Symbol naming rules
3.5.2. Variables
3.5.3. Numeric constants
3.5.4. Assembly time substitutionof variables
3.5.5. Labels
3.5.6. Local labels
3.6. Expressions, literals, and operators
3.6.1. String expressions
3.6.2. String literals
3.6.3. Numeric expressions
3.6.4. Numeric literals
3.6.5. Floating-point literals
3.6.6. Register-relative andprogram-relative expressions
3.6.7. Logical expressions
3.6.8. Logical literals
3.6.9. Operator precedence
3.6.10. Unary operators
3.6.11. Binary operators
3.7. Diagnostic messages
3.7.1. Interlocks
3.8. Using the C preprocessor
4. ARM and Thumb instructions
4.1. Instruction summary
4.2. Memory access instructions
4.2.1. Address alignment
4.2.2. LDR and STR (zero,immediate, or pre-indexed immediate offset)
4.2.3. LDR and STR (post-indexedimmediate offset)
4.2.4. LDR and STR (registeror pre-indexed register offset)
4.2.5. LDR and STR (post-indexedregister offset)
4.2.6. LDR (PC-relative)
4.2.7. PLD
4.2.8. LDM and STM
4.2.9. PUSH and POP
4.2.10. SWP and SWPB
4.3. General data processing instructions
4.3.1. Flexible second operand
4.3.2. ADD, SUB, RSB, ADC,SBC, and RSC
4.3.3. AND, ORR, EOR, andBIC
4.3.4. CLZ
4.3.5. CMP and CMN
4.3.6. MOV and MVN
4.3.7. TST and TEQ
4.3.8. ASR, LSL, LSR, ROR,and RRX
4.4. Multiply instructions
4.4.1. MUL and MLA
4.4.2. UMULL, UMLAL, SMULL,and SMLAL
4.4.3. SMULxy andSMLAxy
4.4.4. SMULWy andSMLAWy
4.4.5. SMLALxy
4.5. Saturating instructions
4.5.1. What saturating means
4.5.2. QADD, QSUB, QDADD,and QDSUB
4.6. Parallel instructions
4.6.1. Parallel add and subtract
4.7. Packing and unpacking instructions
4.7.1. SBFX and UBFX
4.8. Branch instructions
4.8.1. B, BL, BX, BLX, andBXJ
4.9. Coprocessor instructions
4.9.1. CDP and CDP2
4.9.2. MCR, MCR2, MCRR, andMCRR2
4.9.3. MRC, MRC2, MRRC andMRRC2
4.9.4. LDC and STC
4.9.5. LDC2 and STC2
4.10. Miscellaneous instructions
4.10.1. BKPT
4.10.2. SWI
4.10.3. MRS
4.10.4. MSR
4.10.5. SMI
4.10.6. NOP
4.11. Pseudo-instructions
4.11.1. ADR pseudo-instruction
4.11.2. ADRL pseudo-instruction
4.11.3. LDR pseudo-instruction
5. Vector Floating-point Programming
5.1. The vector floating-point coprocessor
5.1.1. VFP architectures
5.2. Floating-point registers
5.2.1. Register banks
5.2.2. Vectors
5.3. Vector and scalar operations
5.3.1. Control of scalar, vector and mixed operations
5.4. VFP and condition codes
5.5. VFP system registers
5.5.1. FPSCR, the floating-point status andcontrol register
5.5.2. FPEXC, the floating-pointexception register
5.5.3. FPSID, the floating-point system IDregister
5.5.4. Modifying individual bits of a VFPsystem register
5.6. Flush-to-zero mode
5.6.1. When to use flush-to-zero mode
5.6.2. The effects of using flush-to-zero mode
5.6.3. Operations not affected by flush-to-zeromode
5.7. VFP instructions
5.7.1. FABS, FCPY, and FNEG
5.7.2. FADD and FSUB
5.7.3. FCMP
5.7.4. FCVTDS
5.7.5. FCVTSD
5.7.6. FDIV
5.7.7. FLD and FST
5.7.8. FLDM and FSTM
5.7.9. FMAC, FNMAC, FMSC,and FNMSC
5.7.10. FMDRR and FMRRD
5.7.11. FMDHR, FMDLR, FMRDH,and FMRDL
5.7.12. FMRS and FMSR
5.7.13. FMRRS and FMSRR
5.7.14. FMRX, FMXR, and FMSTAT
5.7.15. FMUL and FNMUL
5.7.16. FSITO and FUITO
5.7.17. FSQRT
5.7.18. FTOSI and FTOUI
5.8. VFP directives andvector notation
5.8.1. VFPASSERT SCALAR
5.8.2. VFPASSERT VECTOR
6. Directives Reference
6.1. Alphabetical list of directives
6.2. Symbol definition directives
6.2.1. GBLA, GBLL, and GBLS
6.2.2. LCLA, LCLL, and LCLS
6.2.3. SETA, SETL, and SETS
6.2.4. RLIST
6.2.5. CN
6.2.6. CP
6.2.7. DN and SN
6.2.8. FN
6.3. Data definition directives
6.3.1. LTORG
6.3.2. MAP
6.3.3. FIELD
6.3.4. SPACE
6.3.5. DCB
6.3.6. DCD and DCDU
6.3.7. DCDO
6.3.8. DCFD and DCFDU
6.3.9. DCFS and DCFSU
6.3.10. DCI
6.3.11. DCQ and DCQU
6.3.12. DCW and DCWU
6.3.13. COMMON
6.3.14. DATA
6.4. Assembly control directives
6.4.1. Nesting directives
6.4.2. MACRO and MEND
6.4.3. MEXIT
6.4.4. IF, ELSE, ENDIF, andELIF
6.4.5. WHILE and WEND
6.5. Frame directives
6.5.1. FRAME ADDRESS
6.5.2. FRAME POP
6.5.3. FRAME PUSH
6.5.4. FRAME REGISTER
6.5.5. FRAME RESTORE
6.5.6. FRAME RETURN ADDRESS
6.5.7. FRAME SAVE
6.5.8. FRAME STATE REMEMBER
6.5.9. FRAME STATE RESTORE
6.5.10. FRAME UNWIND ON
6.5.11. FRAME UNWIND OFF
6.5.12. FUNCTION or PROC
6.5.13. ENDFUNC or ENDP
6.6. Reporting directives
6.6.1. ASSERT
6.6.2. INFO
6.6.3. OPT
6.6.4. TTL and SUBT
6.7. Instruction set and syntax selectiondirectives
6.7.1. ARM and CODE32
6.7.2. THUMB
6.7.3. CODE16
6.8. Miscellaneous directives
6.8.1. ALIGN
6.8.2. AREA
6.8.3. END
6.8.4. ENTRY
6.8.5. EQU
6.8.6. EXPORT or GLOBAL
6.8.7. EXPORTAS
6.8.8. EXTERN
6.8.9. GET or INCLUDE
6.8.10. IMPORT
6.8.11. INCBIN
6.8.12. KEEP
6.8.13. NOFP
6.8.14. REQUIRE
6.8.15. REQUIRE8 and PRESERVE8
6.8.16. RN
6.8.17. ROUT
Glossary

List of Figures

4.1. ROR
4.2. RRX
5.1. VFP register banks

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Product Status

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Revision History
Revision B April2005 Release for RVDK v2.2
Copyright © 2005 ARM Limited. All rights reserved. ARM DUI 0283B
Non-Confidential