Design Simulation Model User Guide Chapter 5. Timing

Chapter 5. Timing

This chapter describes timing issues and some of the facilities provided to aid the annotation process. It contains the following sections:

About the timing shell
Multiple timing paths
SDF annotation
Interconnect delays
Use of negative timing checks
STA and HDL annotated simulation differences
Limitations of the timing model.

Note

This chapter is applicable for:

timing sign-off with a non-synthesizable processor
some preliminary timing simulation with a synthesizable processor.

This chapter is not applicable if you want to do timing sign-off for a synthesizable processor because the DSM is not suitable for this. You must use a dedicated SOM instead.

Copyright © 2005 ARM Limited. All rights reserved.	ARM DUI 0302A
Non-Confidential
PDF version