1.1.1. Features of ARM DSMs

Table 1.1 shows the main features of ARM DSMs.

Table 1.1. ARM DSM features

Full device functionalityThe DSM fully matches the architecture and functionality of the RTL model.
Phase accuracyYou can expect the DSM to exhibit the same intra-cycle timing as the RTL model.
Register visibility

The DSM might provide debug visibility of the registers within models of processors, depending on the processor. The register set of a core for all modes represented in the architecture might be visible in a special layer of Verilog hierarchy inside the DSM, depending on the processor. These registers are available for tracing in your simulation.


  • Some out-of-order processors might not offer any visibility.

  • This feature does not apply if your ARM product is not a processor, or does not include a processor.

Cache and memory size configuration

You can configure the size of the cache, or TCM, for each particular DSM instance, where applicable.


This feature does not apply if your ARM product has no such configuration, or where your DSM generation flow does not support multiple configurations.


Some DSMs also provide a built-in disassembler. The availability of the disassembler varies from core to core and depends on the availability of a suitable execution tracer built into the RTL of the core from which the DSM is derived.


This feature does not apply if your ARM product does not have a disassembler.

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