Appendix A. Revisions

This appendix describes the technical changes between released issues of this book.

Table A.1. Issue A

First release--

Table A.2. Differences between issue A and issue B

Deleted Chapter 3, Timing IssuesChapter 3r1p0
Removed descriptions relating to VHDLThroughout bookr1p0

Table A.3. Differences between issue B and issue C

Removed ‘ARM publications’ section because it incorrectly referred to two documents that do not yet exist.Additional readingr1p0
Changed description for ‘Register visibility’ to indicate that visibility might be possible, but that it is not guaranteed. Also changed the description to indicate that for some out-of-order processors, visibility might not be possible at all.Features of ARM DSMsr1p0
Caches and registersr1p0

Table A.4. Differences between issue C and issue D

Revised description to clarify that certain functionality, such as Tarmac trace, does not apply for all ARM products.Features of ARM DSMsr1p0
Added notes to some features to clarify that these do not always apply.Features of ARM DSMsr1p0
Clarified that this process might not apply.How to extract the DSMr1p0
Modified search paths.SystemVerilog DPI Interfacer1p0

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