RealView Emulation Baseboard User Guide: 2.3.1. Tile status messages displayed on the LCD

2.3.1. Tile status messages displayed on the LCD

The firmware loaded by default into the baseboard FPGA detects the tiles present at power-on and outputs the status to the character LCD as listed in Table 2.5.

Caution

The default FPGA image is for the CT926EJ-S. See Loading FPGA and PLD images for details on loading the FPGA image for other Core Tiles.

Table 2.5. Tile status messages displayed on character LCD

Tile site 1	Tile site 2	Message displayed
No tile fitted	No tile fitted	TS1 Fit CT926EJS TS2 Optional
No tile fitted	Core Tile or Logic Tile present	TS1 Fit CT926EJS TS2 present
CT926EJ-S Core Tile present	No tile fitted	TS1 OK CT926EJS TS2 Optional
CT926EJ-S Core Tile present	Core Tile or Logic Tile present	TS1 OK CT926EJS TS2 Optional

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