The test points and test connectors are shown in Figure A.12. The functions of the test points on the baseboard are summarized in Table A.12.
Test points not listed are not present or are reserved for manufacturing use only.
Table A.12. Test point functions
Test point | Signal | Function |
|---|---|---|
TP1 | VBATT | Backup battery voltage |
TP2 | OSCCLK0 | Output from programmable oscillator 0 |
TP3 | GLOBALCLKOUTTP1 | Global clock output |
TP4 | REFCLK24MHZ | 24MHz reference from OSC0 |
TP5 | OSCCLK1 | Output from programmable oscillator 1 |
TP6 | OSCCLK2 | Output from programmable oscillator 2 |
TP7 | OSCCLK3 | Output from programmable oscillator 3 |
TP8 | OSCCLK4 | Output from programmable oscillator 4 |
| TP9 | REFCLK32K | 32.768kHz reference clock |
| TP10 | INTCLK | Test clock from USB debug logic |
| TP11 | EnRST | Reset output signal related to USB debug test |
| J7 | DXP and DXN | Temperature monitor. Connect a meter to this voltage to monitor the FPGA operating temperature. (Refer to the Xilinx data sheet for more information.) |
| TP14 | - | Not present |
| TP15 | RAW_CLK | Clock signal from USB debug interface |
| TP16 | 12VDC | 12V DC supply |
| TP17 | 5V_ANALOG | 5V DC supply to analog circuitry |
| TP18 | 1V8 | 1.8V supply for PLDs, flash memory, and PISMO memory boards |
| TP19 | 1V5 | 1.5V supply for FPGA and DDR memory |
| TP20 | VDDCORE25_SW1 | 2.5V supply to DDR |
| TP22 | GLOBALCLKINTP1 | Global clock input |
TP23 | GLOBALCLKINTP2 | Global clock input |
TP24 | GLOBALCLKOUTTP2 | Global clock output |
TP30 | VDDCORE18_SW | 1.8V power supply to USB debug PLD |
The links are shown in Figure A.13. The functions of the links are summarized in Table A.13.
Table A.13. Links
| Link | Function |
|---|---|
| J34 | Smart Card voltage select. Fit link across AB for 3.3V operation or across BC for 5V operation. Omit link for 1.8V Smart Cards. |
| J47 | Used for manufacturing test only |
| J48 | Force on. Connect link to force the power on and prevent the standby push button from switching the power off. |
| LK1 | Microphone voltage. Fit link across AB to connect microphone bias voltage to microphone 1 or fit BC to connect voltage to microphone 2. Omit link if microphone does not require bias voltage. |
| LK2 | Character LCD voltage (fitted at manufacture). Link fitted on AB for 5V devices or BC for 3.3V devices. This link is fitted at manufacture and must not be changed. |
| LK4-8 | Manufacturing test. Remove link to disconnect switching regulator outputs. Remove LK4 to disconnect the 5V regulator for the analog circuitry Remove LK5 to disconnect the 5V regulator for the digital logic Remove LK6 to disconnect the 3.3V regulator Remove LK7 to disconnect the 1.8V regulator Remove LK8 to disconnect the 1.5V regulator |
| LK9 | NOR flash VCDQ voltage select. Link fitted to BC if the flash memory devices fitted to the board are L30 parts that operate at 1.8V. Link fitted to AB for all other parts. This link is fitted at manufacture and must not be changed. |
| R410 | Manufacturing test link. Selects 12MHz external clock for USB interface This link is not fitted for production boards. |
| R223-R225 | Links DSR to DTR for serial ports 1 to 3. This link is fitted as standard on production boards. |
The switches and indicators are shown in Figure A.14. The functions of the switches and indicators are summarized in Table A.15 and Table A.14.
Table A.14. Indicators
| LED | Function |
|---|---|
| D1 | Fused 5V OK |
| D2, D5 | Tile site 1 detect |
| D4 | CONFIG LED |
| D6, D7 | Tile site 2 detect |
| D8 | Reset switch |
| D9 | Indicator for user push button switch |
| D10 | Indicator for FPGA config push button switch |
| D12 | USB debug busy |
| D13 | USB debug on |
| D[21:14] | User LEDs (LED[7:0]) |
| D25 | On/Standby |
| D29 | 3.3V OK |
| D30 | USB1 power |
| D31 | USB2 power |
| D35 | Global done (GLOBAL_DONE), all FPGAs in the system have been configured |
| D36 | Local done (LOCAL_DONE), the baseboard FPGA has been configured |
| D37 | USB 3 power |
Table A.15. Switches
| Switch | Function |
|---|---|
| S1 | Config switch. Slide switch to ON position to put the system into JTAG configuration mode. |
| S2 | Reset push button |
| S3 | General-purpose push button |
| S4 | Reconfigure FPGA push button |
| S5 | Not fitted |
| S6 | User switches USERSW[7:0] |
| S7 | Power/standby push button |
| S8 | Boot switches BOOTSEL[7:0] |
| S9 | Not fitted |
| S10 | FPGA image select switches CFG_SEL[4:1] |
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