RealView Emulation Baseboard User Guide: 4.3.7. SYS

4.3.7. SYS_CONFIGDATAx

These registers (at 0x10000028 and 0x1000002C) are used to control configuration of the system clocks.

Note

The function of these registers might be different for the combination of boards that you are using. Read the application note for your system for any changes to this register area.

Table 4.9 and Table 4.10 describe the bit assignments for the configuration registers for a Core Tile CT1136JF-S.

Table 4.9. Init register 1, SYS_CONFIGDATA1 bit assignment

Bits	Access	Description
[31:30]	Reserved. Use read-modify-write to preserve value.
[29:24]	Read-only	USERIN[5:0]
[23:17]	Reserved. Use read-modify-write to preserve value.
[16]	Read/Write	Internal RAM enable: 0 = disabled 1 = enabled.
[15:8]	Read/Write	PLLFBDIV[7:0]
[7]	Reserved. Use read-modify-write to preserve value.
[6:4]	Read/Write	HCLK divider (the default value depends on the setting of switch SW-8)
[3]	Reserved. Use read-modify-write to preserve value.
[2]	Read/Write	VINITHI: 0 = vectors at `0x0` 1 = vectors at `0xFFFF0000`.
[1]	Read-only	PLLBYPASS
[2]	Read/Write	PLLBYPASS (takes effect only after reset): 0 = off 1 = on.

Table 4.10. Init register 2, SYS_CONFIGDATA2 bit assignment

Bits	Access	Description
[31]	Reserved. Use read-modify-write to preserve value.
[30]	Read-only	ENIRW_SYNC (default is 0)
[29]	Read-only	ENPD_SYNC (default is 0)
[28]	Read-only	HCLK_SYNC (default is 0)
[27]	Read-only	IRW_SYNC (default is 0)
[26]	Read-only	PD_SYNC (default is 0)
[25:20]	Read/Write	HCLKE (default is 3, depends on setting of switch SW-8)
[19:14]	Read/Write	HCLK1 (default is 1)
[13:8]	Read/Write	CLK (default is 0)
[7:0]	Reserved. Use read-modify-write to preserve value.

Copyright © 2005-2011 ARM Limited. All rights reserved.	ARM DUI 0303E
Non-Confidential
PDF version